Low-Voltage High-Linearity Differential Input Buffer with CurrentAmplifier Feed-Forward Compensation for High-Speed ADCs

Author(s):  
Zhengbo Huang ◽  
Hong Zhang ◽  
Ting Li ◽  
Daiguo Xu
2014 ◽  
Vol 678 ◽  
pp. 497-500
Author(s):  
Xing Fa Huang ◽  
Rong Bin Hu ◽  
Liang Li

With respect to the application of high-speed, high-resolution A/D converter, the design and implementation of a CMOS input buffer is introduced. The buffer features high-speed and high-linearity. Its performances have been verified in a 14-bit 250MSPS pipelined A/D converter which is developed in 0.18um CMOS-based process technology. The simulation shows that the SFDR of the buffer is up to 104dB at an input clock of 250MHz with an input signal of 25MHz.


Nanophotonics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 1765-1773
Author(s):  
Yi Zhang ◽  
Jianfeng Gao ◽  
Senbiao Qin ◽  
Ming Cheng ◽  
Kang Wang ◽  
...  

Abstract We design and demonstrate an asymmetric Ge/SiGe coupled quantum well (CQW) waveguide modulator for both intensity and phase modulation with a low bias voltage in silicon photonic integration. The asymmetric CQWs consisting of two quantum wells with different widths are employed as the active region to enhance the electro-optical characteristics of the device by controlling the coupling of the wave functions. The fabricated device can realize 5 dB extinction ratio at 1446 nm and 1.4 × 10−3 electrorefractive index variation at 1530 nm with the associated modulation efficiency V π L π of 0.055 V cm under 1 V reverse bias. The 3 dB bandwidth for high frequency response is 27 GHz under 1 V bias and the energy consumption per bit is less than 100 fJ/bit. The proposed device offers a pathway towards a low voltage, low energy consumption, high speed and compact modulator for silicon photonic integrated devices, as well as opens possibilities for achieving advanced modulation format in a more compact and simple frame.


Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1873
Author(s):  
Chen Cai ◽  
Xuqiang Zheng ◽  
Yong Chen ◽  
Danyu Wu ◽  
Jian Luan ◽  
...  

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.


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