A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic

2010 ◽  
Vol E93-A (12) ◽  
pp. 2755-2757
Author(s):  
Jin-Fa LIN ◽  
Yin-Tshung HWANG ◽  
Ming-Hwa SHEU
Keyword(s):  
Low Complexity ◽  
Dual Mode ◽  
Flip Flop

Low Complexity and Low Power Sense-Amplifier Based Flip-Flop Design

2019 ◽  
Vol E102.C (11) ◽  
pp. 833-838
Author(s):  
Po-Yu KUO ◽  
Chia-Hsin HSIEH ◽  
Jin-Fa LIN ◽  
Ming-Hwa SHEU ◽  
Yi-Ting HUNG
Keyword(s):  
Low Power ◽  
Low Complexity ◽  
Flip Flop ◽  
Sense Amplifier

Dual-Mode Low-Complexity Codebook Searching Algorithm and VLSI Architecture for LTE/LTE-Advanced Systems

2013 ◽  
Vol 61 (14) ◽  
pp. 3545-3562 ◽  
Author(s):  
Yi-Hsuan Lin ◽  
Yu-Hao Chen ◽  
Chun-Yuan Chu ◽  
Cheng-Zhou Zhan ◽  
An-Yeu Wu
Keyword(s):  
Vlsi Architecture ◽  
Low Complexity ◽  
Dual Mode ◽  
Lte Advanced

scholarly journals Dual-Mode Index Modulation Aided OFDM With Constellation Power Allocation and Low-Complexity Detector Design

IEEE Access ◽  
2017 ◽  
Vol 5 ◽  
pp. 23871-23880 ◽  
Author(s):  
Xuekun Zhang ◽  
Hongxia Bie ◽  
Qianwen Ye ◽  
Chunyang Lei ◽  
Xianfeng Tang
Keyword(s):  
Power Allocation ◽  
Low Complexity ◽  
Dual Mode ◽  
Mode Index ◽  
Index Modulation ◽  
Detector Design

scholarly journals Low Power and Low Complexity Flip-Flop Design using MIFGMOS

2018 ◽  
Vol 7 (3.1) ◽  
pp. 183
Author(s):  
U Ragavendran ◽  
M Ramachandran
Keyword(s):  
Low Power ◽  
Cochlear Implants ◽  
Low Complexity ◽  
Floating Gate ◽  
Cmos Process ◽  
Process Technology ◽  
Process Data ◽  
Flip Flop ◽  
Passive Devices ◽  
Sequential Logic

Sequential logic is essential in many applications as data processing for speech recognition in cochlear implants. In this paper, a family of latches based on floating-gate MOS (FGMOS) transistors is presented. This family takes advantage on the fact that FGMOS logics process data using mostly passive devices, achieving small area and low-power, requirements of modern electronics. Post-layout SPICE simulations from an ON-Semiconductors 0.5 µm CMOS process technology shows improvements over conventional CMOS logic families, making FGMOS latches ideal for low-power applications.  

A Low Power PFD and Dual Mode CP with Small Current Mismatch for PLL Application

2012 ◽  
Vol 457-458 ◽  
pp. 1178-1182 ◽  
Author(s):  
Cao Yu ◽  
Min Su Kim ◽  
Hyung Chul Kim ◽  
Youn Goo Yang
Keyword(s):  
High Speed ◽  
Dead Zone ◽  
Charge Pump ◽  
Cmos Process ◽  
Dual Mode ◽  
Small Current ◽  
Flip Flop ◽  
Voltage Range ◽  
Frequency Detector ◽  
Reset Time

A high speed Phase-Frequency Detector (PFD) and Charge Pump (CP) are implemented using 0.13µm CMOS process with 1.2 V supply. The PFD is implemented with TSPC (True Single-Phase Clock) and positive edge triggered D flip-flop. Its polarity can be changed by setting the port. The dead zone problem is solved using an additional reset time. A single charge pump is implemented with two compensators. Dual mode CP design makes the charge pump much more flexible in applications. The current mismatch for the two modes is below 4.9 % within the voltage range of from 0.2 to 1.0 V.

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