A low power dual-mode pulse triggered flip-flop using pass transistor logic

In this paper a novel technique is proposed based on the comparison between Conventional Conditional Data Mapping Flip-flop and Clock Pair Shared D flip flop(CPSFF) here we are checking the working of CDMFF and the conventional D Flip-flop. Due to the immense growth in nanometer technology the SOC is became the future concept of the modern electronics the number of clock transistors are also considerably increased. In this paper we propose a new system which will considerably reduce the number of transistor which will lead to the reduction in clocking power which will improve the overall power consumption.Our proposed which is designed using Pass Transistor Logic (LCPTFF) Low Power Clocked Pass Transistor Flip-Flop system is showing much better output than all other designs as mentioned in the tabulation.The simulations are done using Microwind& DSCH analysis software tools and the result between all those types are listed below.

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Design and comparative analysis of D-Flip-flop using conditional pass transistor logic for high-performance with low-power systems

Microprocessors and Microsystems ◽

10.1016/j.micpro.2019.05.004 ◽

2019 ◽

Vol 68 ◽

pp. 92-101 ◽

Cited By ~ 3

Author(s):

R. Murugasami ◽

U.S. Ragupathy

Keyword(s):

Comparative Analysis ◽

Power Systems ◽

Low Power ◽

High Performance ◽

Flip Flop ◽

Pass Transistor ◽

Pass Transistor Logic

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A Low Power, High Speed 18-Transitor True Single-Phase Clocking D Flip- Flop Design In 90nm Cmos Technology

International Journal of Innovative Technology and Exploring Engineering - Special Issue ◽

10.35940/ijitee.k2531.0981119 ◽

2019 ◽

Vol 8 (11) ◽

pp. 3258-3262

Keyword(s):

Low Power ◽

High Speed ◽

Single Phase ◽

Average Power ◽

Circuit Complexity ◽

Cmos Technology ◽

Flip Flop ◽

Average Power Consumption ◽

Pass Transistor ◽

Pass Transistor Logic

In this paper the authors came up with a contemporary low power, high-speed 18- transistor true singlephase clocking D flip-flop (FF) design using complementary pass-transistor logic. This design is a master-slave-type logic structure and hybrid logic design consisting of complementary pass-transistor logic style and static CMOS logic style. In order to reduce the number of transistors and to simplify the circuit complexity complementary pass-transistor logic style is used. In this design state transition is faster in the slave latch which enhances time performance using a virtual VDD technique. The circuit is designed using GPDK 90nm CMOS technology and the simulation results show better performance indices such as average power consumption, clock- to-Q delay, data-to-Q delay, PDP and area of utilization.

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