A Low Power PFD and Dual Mode CP with Small Current Mismatch for PLL Application

2012 ◽  
Vol 457-458 ◽  
pp. 1178-1182 ◽  
Author(s):  
Cao Yu ◽  
Min Su Kim ◽  
Hyung Chul Kim ◽  
Youn Goo Yang
Keyword(s):  
High Speed ◽  
Dead Zone ◽  
Charge Pump ◽  
Cmos Process ◽  
Dual Mode ◽  
Small Current ◽  
Flip Flop ◽  
Voltage Range ◽  
Frequency Detector ◽  
Reset Time

A high speed Phase-Frequency Detector (PFD) and Charge Pump (CP) are implemented using 0.13µm CMOS process with 1.2 V supply. The PFD is implemented with TSPC (True Single-Phase Clock) and positive edge triggered D flip-flop. Its polarity can be changed by setting the port. The dead zone problem is solved using an additional reset time. A single charge pump is implemented with two compensators. Dual mode CP design makes the charge pump much more flexible in applications. The current mismatch for the two modes is below 4.9 % within the voltage range of from 0.2 to 1.0 V.

scholarly journals Phase Frequency Detector and Charge Pump for Low Jitter PLL Applications

2018 ◽  
Vol 8 (6) ◽  
pp. 4120
Author(s):  
Sung Sik Park ◽  
Ju Sang Lee ◽  
Sang Dae Yu
Keyword(s):  
Circuit Simulation ◽  
Pulse Height ◽  
Charge Pump ◽  
Cmos Process ◽  
Charge Pumps ◽  
Current Matching ◽  
Low Jitter ◽  
A New Technique ◽  
Charge Pump Circuit ◽  
Frequency Detector

In this paper a new technique is presented to improve the jitter performance of conventional phase frequency detectors by completely removing the unnecessary one-shot pulse. This technique uses a variable pulse-height circuit to control the unnecessary one-shot pulse height. In addition, a novel charge-pump circuit with perfect current-matching characteristics is used to improve the output jitter performance of conventional charge pumps. This circuit is composed of a pair of symmetrical pump circuits to obtain a good current matching. As a result, the proposed charge-pump circuit has perfect current-matching characteristics, wide output range, no glitch output current, and no jump output voltage. In order to verify such operation, circuit simulation is performed using 0.18 μm CMOS process parameters.

scholarly journals Time Amplifier Based Bang-Bang Phase Frequency Detector in 0.18μm CMOS Technology

2019 ◽  
Vol 9 (1S3) ◽  
pp. 85-89
Keyword(s):  
Dead Zone ◽  
Cmos Technology ◽  
Maximum Frequency ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
Sense Amplifier ◽  
Time Amplifier ◽  
Frequency Detector ◽  
Cmos Implementation

A CMOS Implementation of Time amplifier (TA) based Bang-Bang Phase Frequency Detector (BBPFD) using Sense amplifier based flip flop (SAFF) is presented in this paper using 0.18μm CMOS technology. A time amplifier based on feedback output generator concept is utilized in minimizing the metastability and increasing the gain of TA which in turn boosts the gain of Phase Frequency Detector (PFD). Also, a modified SAFF was built in CMOS 0.18μm technology at 1.8V which further reduces the hysteresis and metastability aspect related to PFD. The proposed PFD works at a maximum frequency of 4GHz consuming 0.46mW of power with no dead zone.

scholarly journals A Broadband High-speed Programmable Multi-modulus Divider Based on CMOS Process

2021 ◽  
Vol 2132 (1) ◽  
pp. 012046
Author(s):  
Muzhen Hao ◽  
Xiaodong Liu ◽  
Zhizhe Liu ◽  
Feng Ji ◽  
Di Sun ◽  
...  
Keyword(s):  
Phase Noise ◽  
High Frequency ◽  
High Speed ◽  
Frequency Divider ◽  
Cmos Process ◽  
Frequency Division ◽  
Frequency Range ◽  
Flip Flop ◽  
Large Bandwidth ◽  
Level 2

Abstract This paper introduces a design of a high-speed programmable multi-modulus divider (MMD) based on 65nm CMOS process. The design adopts the cascade structure of 7 level 2/3 frequency dividers, and expands the frequency division range by adjusting the number of cascade stages, so as to achieve a continuous frequency division ratio of 16 to 255. Among them, the first level 2/3 frequency divider adopts the D flip-flop design of CML (current mode logic) structure, the second level 2/3 frequency divider adopts the D flip-flop design of E-TSPC (extended true-single-phase-clock) structure. The whole circuit realizes the working frequency range of 13∼18GHz high frequency and large bandwidth. This design has completed layout drawing and parasitic parameter extraction simulation. The simulation results show that the operating frequency range of the circuit can reach 13∼18GHz. When the input signal is 18GHz and the frequency division ratio is 255, the phase noise is about -135dBc/Hz@1kHz. It has the advantages of high frequency, large bandwidth, and low phase noise.

Design a Phase Frequency Detector

2013 ◽  
Vol 380-384 ◽  
pp. 3198-3203
Author(s):  
Xue Mei Lei ◽  
Xiao Dong Xing ◽  
Xue Dong Ding
Keyword(s):  
Power Consumption ◽  
Core Area ◽  
Operating Frequency ◽  
Cmos Process ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
High Frequencies ◽  
The Core ◽  
Input Signals ◽  
Frequency Detector

This paper describes a phase frequency detector application using 0.18μm CMOS process. In order to cover the high frequencies of input signals, TSPC D flip-flop structure are applied. The core area of proposal phase frequency detector is 60 μm×50 μm. The simulating results show that rang of operating frequency is from 500kHz to 500MHz and the power consumption is 0.722mW under a 1.8V supply.

High-Speed Low-Power Bulk-Controlled Sense-Amplifier D Flip-Flop

2015 ◽  
Vol 713-715 ◽  
pp. 1042-1047
Author(s):  
Xiao Ying Deng ◽  
Yan Yan Mo ◽  
Jian Hui Ning
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Large Scale ◽  
Supply Voltage ◽  
Operating Conditions ◽  
Cmos Process ◽  
Flip Flop ◽  
Sense Amplifier ◽  
Operation Speed ◽  
Circuits Vlsi

With the development of digital very large scale integrated circuits (VLSI), how to reduce the power dissipation and improve the operation speed are two aspects among the most concerned fields. Based on sense amplifier technology and bulk-controlled technique, this paper proposes a bulk-controlled sense-amplifier D flip-flop (BCSADFF). Firstly, this flip-flop can change the threshold voltage of the NMOS by inputting control signals from the substrate so as to control the operating current. Secondly, the traditional RS flip-flop composed of two NAND gates is improved to a couple of inverters based on pseudo-PMOS dynamic technology. Therefore, the proposed BCSADFF can both effectively reduce the power dissipation and improve the circuit speed. Thirdly, the designed BCSADFF can work normally with ultra-dynamic voltage scaling from 1.8 V to 0.6V for SMIC 0.18-um standard CMOS process. Lastly, the Hspice simulation result shows that, compared with the traditional sense-amplifier D flip-flop (SADFF), the power dissipation of the BCSADFF is significantly reduced under the same operating conditions. When the power supply voltage is 0.9V, the power dissipation and delay of the SADFF is 6.54uW and 0.386ns while that of the proposed BCSADFF is 2.09uW and 0.237ns.

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