scholarly journals Optimisation of scheduled tasks by real-time measurement and correlation

2020 ◽  
pp. 36-43
Author(s):  
Berkay Saydam ◽  
Cem Orhan ◽  
Niyazi Toker ◽  
Mansur Turasan
Keyword(s):  
Real Time ◽  
Functional Safety ◽  
Worst Case ◽  
System Cost ◽  
Simulation Tools ◽  
Real Time Measurement ◽  
Real Hardware ◽  
Execution Times ◽  
Time Critical ◽  
Time Systems

For functional safety, the scheduler should perform all time critical tasks in an order and within predefined deadlines in embedded systems. Scheduling of time critical tasks is determined by estimating their worst-case execution times. To justify the model design of task scheduling, it is required to simulate and visualise the task execution and scheduling maps. This helps to figure out possible problems before deploying the schedule model to real hardware. The simulation tools which are used by companies in an industry perform scheduling simulation and visualisation of all time critical tasks to design and verify the model. All of them lack the capability of comparing simulation results versus real results to achieve the optimised scheduling design. This sometimes leads the overestimated worst-case execution times and increased system cost. The aim of our study is to decrease the system cost with optimisation of scheduled tasks via using the static analysing method.   Keywords: Schedule visualisation, scheduler optimisation, functional safety, real-time systems, scheduler.

scholarly journals PSO based optimization of worst-case execution time for ASIP application

2018 ◽  
Vol 7 (3.3) ◽  
pp. 252
Author(s):  
Mood Venkanna ◽  
Rameshwar Rao ◽  
P Chandra Sekhar
Keyword(s):  
Real Time ◽  
Upper Bounds ◽  
Real Time Systems ◽  
Worst Case ◽  
Reconfigurable Processor ◽  
Worst Case Execution Time ◽  
Execution Times ◽  
Hard Real Time ◽  
Time Systems ◽  
Time Bounds

Industrial requires hard real-time systems for safety and critical applications like automotive, Aeronautics, manufacturing control and train industries. Hard Real-Time Systems’ embedded controllers are with expectation of complete the tasks within a certain time bounds reliably including task scheduling. The estimation of upper bound limits corresponding to the execution times is often termed as the Worst-Case Execution Times (WCETs). It is an essential step in developing and validating the hard real-time systems. Particularly, the upper bounds need to satisfy these constraints related to the execution times. However, it is often not feasible many times to set upper bounds on execution times for programs. In present work, the problem of choosing reconfigurable Custom Instructions (CIs) is accomplished by optimizing the WCET corresponding to an application. This issue is designed using Particle Swarm Optimization (PSO) based program for a path analysis. The work emphasizes on the effectiveness of optimizing the WCET when applied to a reconfigurable processor. It evaluates a compound application of multimedia with a host of reconfigurable CIs corresponding to a number of hardware parameters.  

Use of Measurements in Worst-Case Execution Time Estimation for Real-Time Systems

2021 ◽  
Author(s):  
Jessica Junia Santillo Costa ◽  
Romulo Silva de Oliveira ◽  
Luis Fernando Arcaro
Keyword(s):  
Real Time ◽  
Execution Time ◽  
Time Estimation ◽  
Real Time Systems ◽  
Worst Case ◽  
Worst Case Execution Time ◽  
Time Systems

A Method for Simultaneously Satisfying Important Constraints and Dependencies for Many Different Types of Processes in Embedded Real-Time Systems

2011 ◽  
Author(s):  
Jia Xu
Keyword(s):  
Real Time ◽  
Computation Time ◽  
Real Time Systems ◽  
Worst Case ◽  
Release Times ◽  
Different Types ◽  
High Assurance ◽  
Run Time ◽  
Soft Deadline ◽  
Time Systems

In most embedded, real-time applications, processes need to satisfy various important constraints and dependencies, such as release times, offsets, precedence relations, and exclusion relations. Embedded, real-time systems with high assurance requirements often must execute many different types of processes with such constraints and dependencies. Some of the processes may be periodic and some of them may be asynchronous. Some of the processes may have hard deadlines and some of them may have soft deadlines. For some of the processes, especially the hard real-time processes, complete knowledge about their characteristics can and must be acquired before run-time. For other processes, prior knowledge of their worst case computation time and their data requirements may not be available. It is important for many embedded real-time systems to be able to simultaneously satisfy as many important constraints and dependencies as possible for as many different types of processes as possible. In this paper, we discuss what types of important constraints and dependencies can be satisfied among what types of processes. We also present a method which guarantees that, for every process, no matter whether it is periodic or asynchronous, and no matter whether it has a hard deadline or a soft deadline, as long as the characteristics of that process are known before run-time, then that process will be guaranteed to be completed before predetermined time limits, while simultaneously satisfying many important constraints and dependencies with other processes.

scholarly journals Tight Evaluation of Real-Time Task Schedulability for Processor’s DVS and Nonvolatile Memory Allocation

Micromachines ◽  
2019 ◽  
Vol 10 (6) ◽  
pp. 371 ◽  
Author(s):  
Sunhwa Nam ◽  
Kyungwoon Cho ◽  
Hyokyung Bahn
Keyword(s):  
Real Time ◽  
Power Saving ◽  
Random Access ◽  
Random Access Memory ◽  
Voltage Scaling ◽  
Real Time Systems ◽  
Access Memory ◽  
Placement Problem ◽  
Worst Case ◽  
Time Systems

A power-saving approach for real-time systems that combines processor voltage scaling and task placement in hybrid memory is presented. The proposed approach incorporates the task’s memory placement problem between the DRAM (dynamic random access memory) and NVRAM (nonvolatile random access memory) into the task model of the processor’s voltage scaling and adopts power-saving techniques for processor and memory selectively without violating the deadline constraints. Unlike previous work, our model tightly evaluates the worst-case execution time of a task, considering the time delay that may overlap between the processor and memory, thereby reducing the power consumption of real-time systems by 18–88%.

scholarly journals Worst-case execution-time analysis for embedded real-time systems

2003 ◽  
Vol 4 (4) ◽  
pp. 437-455 ◽  
Author(s):  
Jakob Engblom ◽  
Andreas Ermedahl ◽  
Mikael Sjödin ◽  
Jan Gustafsson ◽  
Hans Hansson
Keyword(s):  
Real Time ◽  
Execution Time ◽  
Real Time Systems ◽  
Time Analysis ◽  
Worst Case ◽  
Worst Case Execution Time ◽  
Time Systems

Novel prioritized LRU circuits for shared cache in computer systems

2020 ◽  
Vol 34 (23) ◽  
pp. 2050242
Author(s):  
Yao Wang ◽  
Lijun Sun ◽  
Haibo Wang ◽  
Lavanya Gopalakrishnan ◽  
Ronald Eaton
Keyword(s):  
Real Time ◽  
High Performance ◽  
Cmos Technology ◽  
Cache Replacement ◽  
Worst Case ◽  
Shared Cache ◽  
Cache Access ◽  
Worst Case Execution Time ◽  
Real Time Applications ◽  
Time Systems

Cache sharing technique is critical in multi-core and multi-threading systems. It potentially delays the execution of real-time applications and makes the prediction of the worst-case execution time (WCET) of real-time applications more challenging. Prioritized cache has been demonstrated as a promising approach to address this challenge. Instead of the conventional prioritized cache schemes realized at the architecture level by using cache controllers, this work presents two prioritized least recently used (LRU) cache replacement circuits that directly accomplish the prioritization inside the cache circuits, hence significantly reduces the cache access latency. The performance, hardware and power overheads due to the proposed prioritized LRU circuits are investigated based on a 65 nm CMOS technology. It shows that the proposed circuits have very low overhead compared to conventional cache circuits. The presented techniques will lead to more effective prioritized shared cache implementations and benefit the development of high-performance real-time systems.

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