scholarly journals A Multi-mode SAR Imaging Chip based on a Dynamically Reconfigurable SoC Architecture Consisting of Dual-operation Engines and Multilayer Switching Network

2018 ◽  
Author(s):  
Teng Long ◽  
Zhu Yang ◽  
Bingyi Li ◽  
Liang Chen ◽  
Zegang Ding ◽  
...  
Keyword(s):  
Real Time ◽  
Integrated Circuit ◽  
Large Scale ◽  
Imaging System ◽  
Processing System ◽  
Switching Network ◽  
Real Time Processing ◽  
Dynamically Reconfigurable ◽  
Sar Imaging ◽  
Multi Mode

With the development of satellite load technology and very-large-scale integrated (VLSI) circuit technology, on-board real-time synthetic aperture radar (SAR) imaging systems have facilitated rapid response to disasters. Limited by severe size, weight, and power consumption constraints, a key challenge of on-board SAR imaging system design is to achieve high real-time processing performance. In addition, with the rise of multi-mode SAR applications, the reconfiguration of the on-board processing system is beginning to receive widespread attention. This paper presents a multi-mode SAR imaging chip with SoC architecture based on the reconfigurable double-operation engines and multilayer switching network. We decompose the commonly used extend chirp scaling (CS) SAR imaging algorithm into 8 types of double-operation engines according to the computing orders, and design a three-level switching network to connect these engines for data transition. The CPU is responsible for engine scheduling based on data flow driven with instructions to implement each part of the CS algorithm. Thus, multi-mode floating-point SAR imaging processing can be integrated into a single Application-Specific Integrated Circuit (ASIC) chip instead of relying on distributed technologies. As a proof of concept, a prototype measurement system with chip-included board is implemented, and the performance of the proposed design is demonstrated on Chinese Gaofen-3 stripmap continuous imaging. A chip requires 9.2 s, 50.6 s and 7.4 s for a stripmap with 16,384×16,384 granularity, multi-channel stripmap with 65.536×8192 granularity and multi-channel scan mode with 32,768×4096 granularity and 6.9 W for the system hardware to process the SAR raw data.

scholarly journals On-chip data organization and access strategy for spaceborne SAR real-time imaging processor

2021 ◽  
Vol 39 (1) ◽  
pp. 126-134
Author(s):  
Shiyu Wang ◽  
Shengbing Zhang ◽  
Xiaoping Huang ◽  
Hao Lyu
Keyword(s):  
Power Consumption ◽  
Real Time ◽  
Imaging System ◽  
Data Organization ◽  
Real Time Processing ◽  
Time Processing ◽  
Chip Data ◽  
Application Systems ◽  
Sar Imaging ◽  
On Chip

Spaceborne SAR(synthetic aperture radar) imaging requires real-time processing of enormous amount of input data with limited power consumption. Designing advanced heterogeneous array processors is an effective way to meet the requirements of power constraints and real-time processing of application systems. To design an efficient SAR imaging processor, the on-chip data organization structure and access strategy are of critical importance. Taking the typical SAR imaging algorithm-chirp scaling algorithm-as the targeted algorithm, this paper analyzes the characteristics of each calculation stage engaged in the SAR imaging process, and extracts the data flow model of SAR imaging, and proposes a storage strategy of cross-region cross-placement and data sorting synchronization execution to ensure FFT/IFFT calculation pipelining parallel operation. The memory wall problem can be alleviated through on-chip multi-level data buffer structure, ensuring the sufficient data providing of the imaging calculation pipeline. Based on this memory organization and access strategy, the SAR imaging pipeline process that effectively supports FFT/IFFT and phase compensation operations is therefore optimized. The processor based on this storage strategy can realize the throughput of up to 115.2 GOPS, and the energy efficiency of up to 254 GOPS/W can be achieved by implementing 65 nm technology. Compared with conventional CPU+GPU acceleration solutions, the performance to power consumption ratio is increased by 63.4 times. The proposed architecture can not only improve the real-time performance, but also reduces the design complexity of the SAR imaging system, which facilitates excellent performance in tailoring and scalability, satisfying the practical needs of different SAR imaging platforms.

Design of Flight Test System Based on 1553B-Bus Real-Time Processing System

2013 ◽  
Vol 774-776 ◽  
pp. 1481-1484
Author(s):  
Yan Lian Zhang
Keyword(s):  
Real Time ◽  
High Performance ◽  
Large Scale ◽  
Processing System ◽  
Flight Test ◽  
Test System ◽  
Real Time Processing ◽  
Time Processing ◽  
Usb Interface ◽  
Logical Control

To satisfy the special requirement of Real-time Processing for 1553B-Bus in large-scale ground experimentation of airborne weapon, the design and realization of 1553B-Bus communication board based on USB-interface and Real-time Processing soft for 1553B-Bus are proposed. The high performance fixed point MSC1210Y5 and the Advanced Communication Engine (ACE) BU-61580 are all used in the design of hardware. The function of logical control is implemented by FPGA. The system achieves data acquisition and real-time processing of 1553B-Bus in ground experimentation; the experiment shows that the system achieves the desired design requirement of experiment testing.

scholarly journals An FPGA-Based Four-Channel 128k-Point FFT Processor Suitable for Spaceborne SAR

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 816
Author(s):  
Yongrui Li ◽  
He Chen ◽  
Yizhuang Xie
Keyword(s):  
Real Time ◽  
Large Scale ◽  
High Efficiency ◽  
Imaging System ◽  
Path Delay ◽  
Real Time Processing ◽  
Time Processing ◽  
Fft Processor ◽  
Adjustment Strategy ◽  
Field Programmable

Spaceborne synthetic aperture radar (SAR) plays an important role in many fields of national defense and the national economy, and the Fast Fourier Transform (FFT) processor is an important part of the spaceborne real-time SAR imaging system. How to meet the increasing demand for ultra-large-scale data processing and to reduce the scale of the hardware platform while ensuring real-time processing is a major problem for real-time processing of on-orbit SAR. To solve this problem, in this study, we propose a 128k-point fixed-point FFT processor based on Field-Programmable Gate Array (FPGA) with a four-channel Single-path Delay Feedback (SDF) structure. First, we combine the radix-23 and mixed-radix algorithms to propose a four-channel processor structure, to achieve high efficiency hardware resources and high real-time performance. Secondly, we adopt the SDF structure combined with the radix-23 algorithm to achieve efficient use of storage resources. Third, we propose a word length adjustment strategy to ensure the accuracy of calculations. The experimental results show that the relative error between the processor and the MATLAB calculation result is maintained at about 10−4, which has good calculation accuracy.

scholarly journals A Real Time Processing system for big data in astronomy: Applications to HERA

2021 ◽  
pp. 100489
Author(s):  
Paul La Plante ◽  
P.K.G. Williams ◽  
M. Kolopanis ◽  
J.S. Dillon ◽  
A.P. Beardsley ◽  
...  
Keyword(s):  
Big Data ◽  
Real Time ◽  
Processing System ◽  
Real Time Processing ◽  
Time Processing

scholarly journals Dynamic management of transactions in distributed real-time processing system

2010 ◽  
Vol 2 (2) ◽  
pp. 161-170 ◽  
Author(s):  
Y. Jayanta Singh ◽  
Yumnam Somananda Singh ◽  
Ashok Gaikwad ◽  
Mehrotra S.C
Keyword(s):  
Real Time ◽  
Processing System ◽  
Dynamic Management ◽  
Real Time Processing ◽  
Time Processing

Implementation of a new real time seismicity detector for the Mayotte crisis

2021 ◽  
Author(s):  
Jean-Marie Saurel ◽  
Lise Retailleau ◽  
Weiqiang Zhu ◽  
Simon Issartel ◽  
Claudio Satriano ◽  
...  
Keyword(s):  
Real Time ◽  
Volcanic Activity ◽  
A Priori ◽  
Processing System ◽  
Activity Level ◽  
Phase Identification ◽  
Real Time Processing ◽  
S Waves ◽  
Hypocentral Location ◽  
New Processing

<p>Seismology is one of the main techniques used to monitor volcanic activity worldwide. Seismicity analysis through several seismic sensor deployments has been used to monitor Mayotte volcano crisis since its beginning in May 2018. Because volcanic activity can evolve rapidly, efficient and accurate seismicity detectors are crucial to assess in real-time the activity level of the volcano and, if needed, to issue timely warnings.</p><p> </p><p><span>Traditional real-time seismic processing software, such as EarthWorm or SeisComP, use phase onset pickers followed by a phase association algorithm to declare an event and proceed with its location. Real-time phase pickers usually cannot identify whether the detected phase is a P or S arrival and this decision or assumption is made by the associator. The lack of S arrival has an obvious impact on the hypocentral location quality. S-phases can also help detection on small earthquakes where weak P-phases can be missed.</span></p><p> </p><p><span>We implemented the deep neural network-based method PhaseNet to identify in real-time seismic P and S waves on 3-component seismometers deployed on Mayotte island. We also built an interface to subsequently process PhaseNet results and send pick objects to EarthWorm. We use EarthWorm binder_ew associator module specifically tuned for PhaseNet </span><span><em>a priori</em></span><span> phase identification to detect and locate the events, which are finally archived in a SeisComP database. We implemented this innovative real-time processing system for the REVOSIMA (Reseau de surveillance Volcanologique et Sismologique de Mayotte) hosted at OVPF (Observatoire Volcanologique du Piton de la Fournaise). We assess the robustness of the algorithm by comparing the results to existing automatic and manually detected seismicity catalogs.</span></p><p> </p><p>We show that the existing SeisComP automatic system is outperformed by our new algorithm, both in number of earthquake detections and location reliability. Our implementation also detects more events than the daily manual data screening. While this promising new processing system was first applied to study the Mayotte seismicity, it can be used in any seismic active zone, of volcanic or tectonic origin. Indeed, it will be installed at Martinique volcanic and seismic observatory later this year.</p>

A Real-Time Processing System Based on Field Programmable Gate Array for Infrared Image

2009 ◽  
Vol 36 (2) ◽  
pp. 307-311
Author(s):  
罗凤武 Luo Fengwu ◽  
王利颖 Wang Liying ◽  
涂霞 Tu Xia ◽  
陈厚来 Chen Houlai
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
Infrared Image ◽  
Processing System ◽  
Real Time Processing ◽  
Time Processing ◽  
Field Programmable ◽  
Gate Array
Sign in / Sign up

Export Citation Format

Share Document