scholarly journals Design of Low-Power SPIHT Decoder Based ECG Compression and Reconstruction System

2021 ◽  
Author(s):  
Vinod Arunachalam ◽  
Kumareshan Natarajan
Keyword(s):  
Low Power ◽  
Real Time ◽  
High Efficiency ◽  
Vlsi Architecture ◽  
Require Time ◽  
Ecg Compression ◽  
Signal Encoding ◽  
And Performance ◽  
Code Complexity ◽  
Spiht Coding

Abstract This article proposes a 1D biomedical signal encoding scheme to allow embedding of metadata and to protect privacy. The compression of ECG signal and its reconstruction is implemented. The design concentrates on an overview of the criteria for safe and effective m-health storage, transmission, and access to medical tests. However, existing architectures for encoding SPIHT are designed to process images/videos. Significant memory and complex sorting algorithms are required for both architectures, and they all require time-consuming tasks that do not apply to mobile ECG applications. On the basis of our previously updated SPIHT coding research, we used flags and bit controls to reduce memory needs and code complexity through a combination of three search processes in one phase. The goal of real-time architecture for mobile ECG applications is therefore to be accomplished. In order first, to solve the disadvantages of the low-encryption speed of coded and complex hardware architectures that characterize previous SPIHT algorithms, we propose a SPIHT coding algorithm that uses several types of state registry files because of its need for dynastic c to attain real-time and performance design objectives. Secondly, a highly piped and efficient VLSI architecture is used to implement a high-efficiency and low-power SPIHT design based on the proposed algorithm.

scholarly journals A Systematic Journal of Multipliers Accuracy and Performance

2019 ◽  
Vol 8 (6S) ◽  
pp. 965-969
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Low Power ◽  
Real Time ◽  
Research Work ◽  
Computer Arithmetic ◽  
Digital Signal ◽  
Systematic Development ◽  
And Performance ◽  
Comprehensive Study

Low power and efficient architecture of computer arithmetic is demanded of real time Digital signal processing. Out of all arithmetic units, the multiplier is most important and frequently used arithmetic component in literature. As we know that there are many multipliers exist in the literature and everyone has his own proc-corns. But there is a gap in literature, no one gets compared all popular multiplier technique at same platform and discuss their advantages and limitations at one place. This research work outlines the most popular five multiplier techniques (like Wallace, modified, Vedic, Russian Peasant and Logarithm) and compares them, highlights merits, demerit for further improvements. This comprehensive study includes the systematic development, compares the latest design of every multiplier and justified that which one is better over other reported multiplier is also highlighted.

Real-Time and Low-Power HEVC Deblocking Filter Architecture Targeting 8K UHD @ 60fps Videos

2020 ◽  
Vol 15 (1) ◽  
pp. 1-9
Author(s):  
Roberta De Carvalho Nobre Palau ◽  
Jones Goebel ◽  
Daniel Palomino ◽  
Guilherme Correa ◽  
Marcelo Porto ◽  
...  
Keyword(s):  
Low Power ◽  
Real Time ◽  
Power Dissipation ◽  
High Efficiency ◽  
Clock Cycle ◽  
Deblocking Filter ◽  
High Efficiency Video Coding ◽  
Normal Filter ◽  
Real Time Processing ◽  
Low Power Dissipation

This paper presents a low-power and high-throughput Deblocking Filter (DBF) hardware architecture for the High Efficiency Video Coding (HEVC) standard. The architecture implements the three HEVC deblocking filtering modes, namely: (i) normal filter, (ii) strong filter and (iii) chroma filter. The designed DBF architecture is able to process 64 samples per clock cycle, considering luminance and chrominance components. The architecture was described in VHDL and synthesized targeting the CMOS standard-cell TSMC 40nm library. The power results were reached with real input samples extracted from the HEVC reference software. Synthesis results show that the DBF design, when running at 124.4MHz, can reach a throughput of 60 frames per second (fps) for a 7680×4320 (8K UHD) video resolution. At this frequency, the DBF design presented a low power dissipation of 4.73mW. The presented DBF hardware surpasses all related works in terms of throughput and power dissipation and is the unique solution able to real-time processing of 8K UHD videos at 60 frames per second.

Research and Design of Traffic Flow Monitoring System Based on Internet of Things

2013 ◽  
Vol 380-384 ◽  
pp. 786-789
Author(s):  
Jun Feng
Keyword(s):  
Internet Of Things ◽  
Real Time ◽  
Traffic Flow ◽  
Monitoring System ◽  
Performance Monitoring ◽  
High Efficiency ◽  
Scheduling Algorithm ◽  
Flow Monitoring ◽  
Real Time Traffic ◽  
And Performance

The existing traffic flow monitoring system has some defects, including dispersed data collection, difficult to accurate and real-time monitor the vehicle motion process, low degree of all types of vehicle identification and limited monitoring performance. In order to solve all the problems above, this paper designs traffic flow monitoring system bases on Internet of Things. Using the core data collected by ZigBee wireless communication technique, the system adopts optimal scheduling algorithm to design the system. Simulation experiments are carried out on the basis of real-time collected by the system. The results show that the system achieves high efficiency and performance monitoring of the vehicle types, real-time classification, vehicle coordinate real-time positioning while operation, automatically receive real-time traffic data, and efficient scheduling.

Real‐time lossless ECG compression for low‐power wearable medical devices based on adaptive region prediction

2014 ◽  
Vol 50 (25) ◽  
pp. 1904-1906 ◽  
Author(s):  
Ke Li ◽  
Yun Pan ◽  
Fangjian Chen ◽  
Kwang‐Ting Cheng ◽  
Ruohong Huan
Keyword(s):  
Low Power ◽  
Real Time ◽  
Medical Devices ◽  
Ecg Compression ◽  
Wearable Medical

scholarly journals Design and Testing of a Power Analyzer Monitor and Programming Device in Industries with a LoRA LPWAN Network

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 453
Author(s):  
Francisco Sánchez-Sutil ◽  
Antonio Cano-Ortega
Keyword(s):  
Low Power ◽  
Real Time ◽  
Loss Rate ◽  
High Efficiency ◽  
Wide Area Networks ◽  
Programming Device ◽  
Average Transmission ◽  
Design And Testing ◽  
Average Information ◽  
Electrical Installation

Electrical installations represent an important part of the industry. In this sense, knowing the state of the electrical installation in real time through the readings of the installed power analyzers is of vital importance. For this purpose, the RS485 bus can be used, which most electrical installations already have. An alternative to the bus wiring and its distance limitation is the use of low-power wide area networks (LPWAN). The long range (LoRa) protocol is ideal for industries due to its low-power consumption and coverage of up to 10 km. In this research, a device is developed to control all the reading and programming functions of a power analyzer and to integrate the device into the LoRa LPWAN network. The power analyzer monitor and programming device (PAMPD) is inexpensive and small enough to be installed in electrical panels, together with the power analyzer, without additional wiring. The information collected is available in the cloud in real time, allowing a multitude of analysis be run and optimization in real time. The results support high efficiency in information transmission with average information loss rate of 3% and a low average transmission time of 30 ms.

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