Design of a Low Power Schottky TTL High-Speed Digital Phase-Locked Loop Integrated Circuit.

1980 ◽  
Author(s):  
James D. Gallia
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
High Speed ◽  
Phase Locked Loop ◽  
Digital Phase

The FPGA-Based Phase-Locked Loop Speed Control System of BLDCM for Magnetically Suspended Control Moment Gyroscope

2011 ◽  
Vol 80-81 ◽  
pp. 1249-1257
Author(s):  
Bang Cheng Han ◽  
Dan He ◽  
Fang Zheng Guo ◽  
Yu Wang ◽  
Bing Nan Huang
Keyword(s):  
Control System ◽  
Integrated Circuit ◽  
High Speed ◽  
Speed Control ◽  
Phase Locked Loop ◽  
Buck Converter ◽  
Current Loop ◽  
Loop Control ◽  
Control Moment Gyroscope ◽  
Control Moment

A phase-locked loop (PLL) control system based on field programmable gates array (FPGA) is proposed through analyzing the model of three-phase unipolar-driven BLDCM (brushless direct current motor) to enhance the reliability and accurate steady-state speed for magnetically suspended control moment gyroscope (MSCMG). The numerical operation module, PLL module and current-loop control module are designed based on FPGA using very-high-speed integrated circuit hardware description language (VHDL) to realize the control law of the digital system. The pulse width modulation (PWM) generating module for Buck converter, the commutation signal generating module for the inverter and ADC module are designed for driving the motor and sampling the current signal. The PLL is analyzed and optimized in the paper and all the modules are verified using the software of ModelSim and the experiments. The simulation and experiment results on BLDCM of MSCMG show that the stability of the motor velocity can reach 0.01% and 0.02% respectively by the PLL technology based on FPGA, which is difficult to be obtained by conventional proportion integral different (PID) speed control.

scholarly journals An all-digital phase-locked loop for high-speed clock generation

2003 ◽  
Vol 38 (2) ◽  
pp. 347-351 ◽  
Author(s):  
Ching-Che Chung ◽  
Chen-Yi Lee
Keyword(s):  
High Speed ◽  
Phase Locked Loop ◽  
Clock Generation ◽  
Digital Phase

A 2.4-GHz low-power all-digital phase-locked loop

2009 ◽  
Author(s):  
Liangge Xu ◽  
Saska Lindfors ◽  
Kari Stadius ◽  
Jussi Ryynanen
Keyword(s):  
Low Power ◽  
Phase Locked Loop ◽  
Digital Phase

scholarly journals A High-Speed Fully Digital Phase-Synchronizer Implemented in a Field Programmable Gate Array Device

2017 ◽  
Vol 24 (3) ◽  
pp. 537-550 ◽  
Author(s):  
Robert Frankowski ◽  
Dariusz Chaberski ◽  
Marcin Kowalski ◽  
Marek Zieliński
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Quantum Physics ◽  
Single Photon ◽  
Photon Number ◽  
Simultaneous Recording ◽  
Wide Frequency Range ◽  
Coincidence Detection ◽  
Clock Period ◽  
Digital Phase

AbstractMost systems used in quantum physics experiments require the efficient and simultaneous recording different multi-photon coincidence detection events. In such experiments, the single-photon gated counting systems can be applicable. The main sources of errors in these systems are both instability of the clock source and their imperfect synchronization with the excitation source. Below, we propose a solution for improvement of the metrological parameters of such measuring systems. Thus, we designed a novel integrated circuit dedicated to registration of signals from a photon number resolving detectors including a phase synchronizer module. This paper presents the architecture of a high-resolution (~60 ps) digital phase synchronizer module cooperating with a multi-channel coincidence counter. The main characteristic feature of the presented system is its ability to fast synchronization (requiring only one clock period) with the measuring process. Therefore, it is designed to work with various excitation sources of a very wide frequency range. Implementation of the phase synchronizer module in an FPGA device enabled to reduce the synchronization error value from 2.857 ns to 214.8 ps.

Low jitter all digital phase locked loop based clock generator for high speed system on-chip applications

2009 ◽  
Vol 96 (11) ◽  
pp. 1183-1189 ◽  
Author(s):  
S. Moorthi ◽  
D. Meganathan ◽  
D. Janarthanan ◽  
P. Praveen Kumar ◽  
J. Raja Paul Perinbam
Keyword(s):  
High Speed ◽  
Phase Locked Loop ◽  
System On Chip ◽  
Clock Generator ◽  
Digital Phase ◽  
Low Jitter ◽  
On Chip
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