Predominance of Blowfish Over Triple Data Encryption Standard Symmetric Key Algorithm for Secure Integrated Circuits Using Verilog HDL

Information Communication Technology (ICT) and Information Security (IS) are playing vital role in the present day communications. Information is prone to side channel attacks at software level where as it is very difficult to hack the information at hardware level. Security is the major concern in the paperless communication and cashless online transactions. This paper aims to implement the most secured Improved Modified Blowfish Algorithm (IMBFA) by incorporating cell substitution using Wave Dynamic Differential Logic (WDDL) and interconnect decomposition in the VLSI Design flow to not to allow the hacker to estimate or predict the key. Proposed IMBFA which can result in high speed, high throughput and effective memory utilization compared to Data Encryption Standard (DES), Triple Data Encryption Standard (TDES), Advanced Encryption Standard (AES) and Blowfish (BF). In this research paper, IMBFA yielded minimum delay as 71.067 ns, frequency of the design as 14.07 MHz, memory utilization as 62.481MB and throughput is 900Mbps compared to AES, TDES and DES algorithms. It is simulated using ModelSim, Synthesized using Leonardo Spectrum and implemented using Verilog HDL.

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Chaotic Rivest-Shamir-Adlerman Algorithm with Data Encryption Standard Scheduling

Bulletin of Electrical Engineering and Informatics ◽

10.11591/eei.v6i3.627 ◽

2017 ◽

Vol 6 (3) ◽

pp. 219-227

Author(s):

Edwin R. Arboleda ◽

Joel L. Balaba ◽

John Carlo L. Espineli

Keyword(s):

Data Encryption ◽

Key Generation ◽

Data Encryption Standard ◽

Rsa Algorithm ◽

Hybrid Data ◽

Symmetric Key ◽

Chaos System ◽

Multiple Keys ◽

Security Device ◽

Provided Examples

Cryptography, which involves the use of a cipher, describes a process of encrypting information so that its meaning is hidden and thus, secured from those who do not know how to decrypt the information. Cryptography algorithms come with the various types including the symmetric key algorithms and asymmetric key algorithms. In this paper, the authors applied the most commonly used algorithm, which is the RSA algorithm together with the Chaos system and the basic security device employed in the worldwide organizations which is the Data Encryption Standard (DES) with the objective to make a hybrid data encryption. The advantage of a chaos system which is its unpredictability through the use of multiple keys and the secrecy of the RSA which is based on integer factorization’s difficulty is combined for a more secure and reliable cryptography. The key generation was made more secure by applying the DES schedule to change the keys for encryption. The main strength of the proposed system is the chaotic variable key generator that chages the value of encrypted message whenever a different number of key is used. Using the provided examples the strength of security of the proposed system was tested and demonstrated.

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Cryptanalytic Attacks on IDEA Block Cipher

Defence Science Journal ◽

10.14429/dsj.66.10798 ◽

2016 ◽

Vol 66 (6) ◽

pp. 582 ◽

Cited By ~ 5

Author(s):

Harish Kumar Sahu ◽

Vikas Jadhav ◽

Shefali Sonavane ◽

R.K. Sharma

Keyword(s):

Block Cipher ◽

Data Encryption ◽

Secret Key ◽

Data Confidentiality ◽

Data Encryption Standard ◽

Financial Application ◽

Time Requirements ◽

International Data ◽

Key Block ◽

Symmetric Key

International data encryption algorithm (IDEA) is a secret key or symmetric key block cipher. The purpose of IDEA was to replace data encryption standard (DES) cipher, which became practically insecure due to its small key size of 56 bits and increase in computational power of systems. IDEA cipher mainly to provide data confidentiality in variety of applications such as commercial and financial application e.g. pretty good privacy (PGP) protocol. Till 2015, no successful linear or algebraic weaknesses IDEA of have been reported. In this paper, author explained IDEA cipher, its application in PGP and did a systematic survey of various attacks attempted on IDEA cipher. The best cryptanalysis result which applied to all keys could break IDEA up to 6 rounds out of 8.5 rounds of the full IDEA cipher1. But the attack requires 264 known plaintexts and 2126.8 operations for reduced round version. This attack is practically not feasible due to above mention mammoth data and time requirements. So IDEA cipher is still completely secure for practical usage. PGP v2.0 uses IDEA cipher in place of BassOmatic which was found to be insecure for providing data confidentiality.

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High throughput FPGA Implementation of Data Encryption Standard with time variable sub-keys

International Journal of Electrical and Computer Engineering (IJECE) ◽

10.11591/ijece.v6i1.pp298-306 ◽

2016 ◽

Vol 6 (1) ◽

pp. 298

Author(s):

Soufiane Oukili ◽

Seddik Bri

Keyword(s):

High Throughput ◽

Data Encryption ◽

Fpga Implementation ◽

Time Variable ◽

Digital Data ◽

Data Encryption Standard ◽

Gate Arrays ◽

Hardware Implementations ◽

Symmetric Key ◽

Legacy Applications

<span lang="EN-US">The Data Encryption Standard (DES) was the first modern and the most popular symmetric key algorithm used for encryption and decryption of digital data. Even though it is nowadays not considered secure against a determined attacker, it is still used in legacy applications. This paper presents a secure and high-throughput Field Programming Gate Arrays (FPGA) implementation of the Data Encryption Standard algorithm. This is achieved by combining 16 pipelining concept with time variable sub-keys and compared with previous illustrated encryption algorithms. The sub-keys vary over time by changing the key schedule permutation choice 1. Therefore, every time the plaintexts are encrypted by different sub-keys. The proposed algorithm is implemented on Xilinx Spartan-3e (XC3s500e) FPGA. Our DES design achieved a data encryption rate of 10305.95 Mbit/s and 2625 number of occupied CLB slices. These results showed that the proposed implementation is one of the fastest hardware implementations with much greater security.</span>

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Cloud based Secure Storage of Files using Hybrid Cryptography and Image Steganography

International Journal of Recent Technology and Engineering - 2 ◽

10.35940/ijrte.f7227.038620 ◽

2020 ◽

Vol 8 (6) ◽

pp. 665-667

Keyword(s):

Data Encryption ◽

Image Steganography ◽

Advanced Encryption Standard ◽

Sensitive Information ◽

Least Significant Bit ◽

Data Encryption Standard ◽

Secure Storage ◽

Symmetric Key ◽

Encryption Algorithms ◽

High Level

Cloud Computing has made it possible to provide individuals as well as organizations with a utility that is costeffective. It empowers businesses by delivering these services using the internet. Files can be shared through the cloud. These files may contain sensitive information that needs to be kept hidden from anonymous users. This is done using cryptographic algorithms. High level of security can be provided using hybrid cryptography to encrypt the data. Advanced Encryption Standard (AES) and Triple Data Encryption Standard (3DES) are the symmetric key encryption algorithms used to secure. An asymmetric key encryption algorithm, Rivest-Shamir-Adleman (RSA) helps in providing a hybrid cryptography model. The security of the key generated can be further enhanced using image steganography method Least Significant Bit (LSB). These issues regarding the security and its challenges will be addressed in this paper and also analyse the measures to handle it.

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High throughput FPGA Implementation of Data Encryption Standard with time variable sub-keys

International Journal of Electrical and Computer Engineering (IJECE) ◽

10.11591/ijece.v6i1.8388 ◽

2016 ◽

Vol 6 (1) ◽

pp. 298 ◽

Cited By ~ 1

Author(s):

Soufiane Oukili ◽

Seddik Bri

Keyword(s):

High Throughput ◽

Data Encryption ◽

Fpga Implementation ◽

Time Variable ◽

Digital Data ◽

Data Encryption Standard ◽

Gate Arrays ◽

Hardware Implementations ◽

Symmetric Key ◽

Legacy Applications

<span lang="EN-US">The Data Encryption Standard (DES) was the first modern and the most popular symmetric key algorithm used for encryption and decryption of digital data. Even though it is nowadays not considered secure against a determined attacker, it is still used in legacy applications. This paper presents a secure and high-throughput Field Programming Gate Arrays (FPGA) implementation of the Data Encryption Standard algorithm. This is achieved by combining 16 pipelining concept with time variable sub-keys and compared with previous illustrated encryption algorithms. The sub-keys vary over time by changing the key schedule permutation choice 1. Therefore, every time the plaintexts are encrypted by different sub-keys. The proposed algorithm is implemented on Xilinx Spartan-3e (XC3s500e) FPGA. Our DES design achieved a data encryption rate of 10305.95 Mbit/s and 2625 number of occupied CLB slices. These results showed that the proposed implementation is one of the fastest hardware implementations with much greater security.</span>

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Routine of Encryption in Cognitive Radio Network

Mehran University Research Journal of Engineering and Technology ◽

10.22581/muet1982.1903.07 ◽

2019 ◽

Vol 38 (3) ◽

pp. 609-618

Author(s):

Asif Raza ◽

Muhammad Tanveer Meeran ◽

Muizzud din

Keyword(s):

Cognitive Radio ◽

Data Transmission ◽

Cognitive Radio Network ◽

Data Transformation ◽

Data Encryption ◽

Radio Networks ◽

Data Encryption Standard ◽

Public Networks ◽

Encryption And Decryption ◽

Symmetric Key

Today data transmission is very important through different channels. Need of network security comes to secure data transformation from one network to another network. As the complexity of the systems and the networks increases, weakness expands and the task of securing the networks is becomes more convoluted. Duty of securing is done by Cryptography techniques. A colossal amount of data is exchanged over public networks like the internet due to immense accommodation. This includes personal details and confidential information. It is important to prevent the data from falling into the wrong hands. So, due to this factor we use cryptography. Encryption and decryption are the basic terms that are used in cryptography. There are few algorithms which used including, AES (Advanced Encryption Standard), DES (Data Encryption Standard), 3DES (Triple Data Encryption Standard) and BLOWFISH. The main contribution of this paper is to provide an algorithm that is useful for data transformation in cognitive radio networks. In this research, we have drawn a new symmetric key technique that is for the usage of cryptography which is helpful to make the data saved from others.

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Design and Implementation of AES Algorithm

International Journal of Recent Technology and Engineering - 2 ◽

10.35940/ijrte.b1075.0782s419 ◽

2019 ◽

Vol 8 (2S4) ◽

pp. 387-390

Keyword(s):

Integrated Circuits ◽

Data Encryption ◽

Advanced Encryption Standard ◽

Second Person ◽

Data Encryption Standard ◽

Aes Algorithm ◽

Zone Control ◽

Application Specific Integrated Circuits ◽

Development Unit ◽

Application Specific

In this paper the Advanced Encryption Standard (AES) was endorsed by the National Institute of Standards and Technology in 2001. It was intended to supplant the maturing Data Encryption Standard (DES) and be valuable for a wide scope of utilizations with differing throughput, zone, control dissemination and vitality utilization necessities .Though they are very adaptable, FPGAs are regularly less effective than Application Specific Integrated Circuits (ASICs); There have been numerous AES executions that attention on acquiring high throughput or low region use, however almost no examination done in the territory of low power or vitality productive based AES; actually, it is uncommon for assessments on power dispersal to be made by any means. This postulation introduces new effective equipment usage to those propelled encryption standard (AES) calculation. Two primary commitments are introduced in this thesis, the initial you quit offering on that one will be a secondary speed 128 odds AES encrypted, and the second person is another 32 odds AES configuration. In 1st commitment An 128 odds circle unrolled sub-pipelined AES encrypted is exhibited. In this encrypted a effective blending to those encryption methodology sub-steps will be executed following relocating them. Those second commitment displays An 32 odds AES plan. In this design, the S-BOX is actualized for inward pipelining Furthermore it is imparted the middle of those principle round and the enter development units. Also, the way development unit is actualized will fill in on the fly What's more previously, parallel with the fundamental round unit. These outlines bring attained higher FPGA (Throughput/Area) effectiveness analyzing to past AES outlines.

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