УНИФИЦИРОВАННАЯ РЕКОНФИГУРИРУЕМАЯ СХЕМА КОММУТАЦИИ БПФ

2020 ◽  
Vol 96 (3s) ◽  
pp. 114-118
Author(s):  
П.С. Поперечный ◽  
И.Ю. Поперечная

Предложен способ вычисления БПФ с унифицированной схемой коммутации от стадии к стадии. Представлено итеративное выражение для аппаратной или программной реализации схемы вычисления. Для предложенных схем описана возможность реконфигурирования для вычисления БПФ различного числа отсчетов, при этом поворотные множители остаются прежними и нет необходимости делать их переменными. The article offers a method for FFT calculation by means of unified communication scheme stage-by-stage. There is an iterating equation for hardware and software implementation. Also, it provides the reconfiguration of schemes by different samples number. The rotating multipliers are the same like in non-reconfigurable (fixed) communication scheme. So, the offered approach does not require additional hardware or software resources.

2019 ◽  
pp. 50-56
Author(s):  
P. S. Poperechny ◽  
I. Yu. Poperechnaya

In the traditional scheme for calculating the fast Fourier transform (FFT), the input arguments for the butterfly computation are switched in a different order depending on the computation stage, which leads to additional resource expenditures in hardware or software implementation. The article offers the method for FFT calculation by means of unified communication scheme stageby‑stage. There is an iterating equation for hardware and software implementation. The equation consists of two‑level loops rather than tree level loop for the traditional scheme. According to the iterating equation the unified communication scheme FFT is provided for both time scale and frequency scale. Also the reconfiguration of schemes by different samples number is provided too. The rotating multipliers are the same like in non‑reconfigurable (fixed) communication scheme. So the offered approach does not required additional hardware or software resources.


2019 ◽  
Author(s):  
Abhishek Verma ◽  
Virender Ranga

Relay node placement in wireless sensor networks for constrained environment is a critical task due to various unavoidable constraints. One of the most important constraints is unpredictable obstacles. Handling obstacles during relay node placement is complicated because of complexity involved to estimate the shape and size of obstacles. This paper presents an Obstacle-resistant relay node placement strategy (ORRNP). The proposed solution not only handles the obstacles but also estimates best locations for relay node placement in the network. It also does not involve any additional hardware (mobile robots) to estimate node locations thus can significantly reduce the deployment costs. Simulation results show the effectiveness of our proposed approach.


Author(s):  
V. Ya. Vilisov

The article proposes an algorithm for solving a linear programming problem (LPP) based on the use of its representation in the form of an antagonistic matrix game and the subsequent solution of the game by an iterative method. The algorithm is implemented as a computer program. The rate of convergence of the estimates of the solution to the actual value with the required accuracy has been studied. The software implementation shows a high speed of obtaining the LPP solution with acceptable accuracy in fractions or units of seconds. This allows the use algorithm in embedded systems for optimal control.


2018 ◽  
pp. 47-53
Author(s):  
B. Z. Shmeylin ◽  
E. A. Alekseeva

In this paper the tasks of managing the directory in coherence maintenance systems in multiprocessor systems with a large number of processors are solved. In microprocessor systems with a large number of processors (MSLP) the problem of maintaining the coherence of processor caches is significantly complicated. This is due to increased traffic on the memory buses and increased complexity of interprocessor communications. This problem is solved in various ways. In this paper, we propose the use of Bloom filters used to accelerate the determination of an element’s belonging to a certain array. In this article, such filters are used to establish the fact that the processor belongs to some subset of the processors and determine if the processor has a cache line in the set. In the paper, the processes of writing and reading information in the data shared between processors are discussed in detail, as well as the process of data replacement from private caches. The article also shows how the addresses of cache lines and processor numbers are removed from the Bloom filters. The system proposed in this paper allows significantly speeding up the implementation of operations to maintain cache coherence in the MSLP as compared to conventional systems. In terms of performance and additional hardware and software costs, the proposed system is not inferior to the most efficient of similar systems, but on some applications and significantly exceeds them.


IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 201806-201822
Author(s):  
Miguel Gayo ◽  
Carlos Santos ◽  
Francisco Javier Rodriguez Sanchez ◽  
Pedro Martin ◽  
Jose A. Jimenez ◽  
...  

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