The False Path:

The article presents world data on the birth of the first children in women with uterine transplants. Explained are the main risks faced by surgeons, donors and recipients during the postoperative period.

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False path detection at transistor level

Proceedings Eleventh International Conference on VLSI Design ◽

10.1109/icvd.1998.646607 ◽

2002 ◽

Author(s):

A. Das ◽

S. Sen ◽

M. Rangan ◽

R. Nayak ◽

Nandakumar

Keyword(s):

False Path ◽

Path Detection

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An Advanced Timing Characterization Method Considering Global False Path

10.1109/imsccs.2006.177 ◽

2006 ◽

Author(s):

Xiaoxiao Liu ◽

Guangsheng Ma ◽

Qiang Sun

Keyword(s):

False Path

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False path and clock scheduling based yield-aware gate sizing

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design ◽

10.1109/icvd.2005.99 ◽

2005 ◽

Cited By ~ 1

Author(s):

Jeng-Liang Tsai ◽

Dong Hyun Baik ◽

C. Chung-Ping Chen ◽

K.K. Saluja

Keyword(s):

Gate Sizing ◽

False Path

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Waiting false path analysis of sequential logic circuits for performance optimization

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) ◽

10.1109/iccad.1998.742902 ◽

2002 ◽

Cited By ~ 1

Author(s):

K. Nakamura ◽

K. Takagi ◽

S. Kimura ◽

K. Watanabe

Keyword(s):

Path Analysis ◽

Performance Optimization ◽

Logic Circuits ◽

Sequential Logic ◽

False Path

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Exact Required Time Analysis Via False Path Detection

Proceedings of the 34th Design Automation Conference ◽

10.1109/dac.1997.597147 ◽

2005 ◽

Cited By ~ 5

Author(s):

Y. Kttkimoto ◽

R.K. Brayton

Keyword(s):

Time Analysis ◽

False Path ◽

Path Detection

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Improve accuracy of delay element by filtering false path for low power desychronized circuits

2011 IEEE International Symposium of Circuits and Systems (ISCAS) ◽

10.1109/iscas.2011.5937698 ◽

2011 ◽

Author(s):

Jun Xu ◽

Xiangku Li

Keyword(s):

Low Power ◽

Delay Element ◽

Improve Accuracy ◽

False Path

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Variation-Aware False Path Analysis Based on Statistical Dynamic Timing Analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2012.2202392 ◽

2012 ◽

Vol 31 (11) ◽

pp. 1684-1697 ◽

Cited By ~ 7

Author(s):

Jongyoon Jung ◽

Taewhan Kim

Keyword(s):

Path Analysis ◽

Timing Analysis ◽

Statistical Dynamic ◽

False Path

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A new approach to the use of satisfiability in false path detection

Proceedings of the 15th ACM Great Lakes symposium on VLSI - GLSVSLI '05 ◽

10.1145/1057661.1057735 ◽

2005 ◽

Cited By ~ 2

Author(s):

Felipe S. Marques ◽

Renato P. Ribas ◽

Sachin Sapatnekar ◽

André I. Reis

Keyword(s):

New Approach ◽

False Path ◽

Path Detection

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False-Path Reduction in Downlink WCDMA Channel Estimation by Threshold Algorithm

Uterus transplant. A road to the future or a false path?

False path detection at transistor level

An Advanced Timing Characterization Method Considering Global False Path

False path and clock scheduling based yield-aware gate sizing

Waiting false path analysis of sequential logic circuits for performance optimization

Exact Required Time Analysis Via False Path Detection

Improve accuracy of delay element by filtering false path for low power desychronized circuits

Variation-Aware False Path Analysis Based on Statistical Dynamic Timing Analysis

A new approach to the use of satisfiability in false path detection

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