Proposals on Lower Thermal Budget Process for In-Ga-Zn-O Thin Film Transistor Using HfO2 Gate Insulators Prepared by Atomic-Layer Deposition at a Temperature of 150°C

Author(s):  
Se-Na Choi ◽  
So-Yeong Na ◽  
Sung-Min Yoon
2011 ◽  
Vol 26 (8) ◽  
pp. 085007 ◽  
Author(s):  
Byeong-Yun Oh ◽  
Young-Hwan Kim ◽  
Hee-Jun Lee ◽  
Byoung-Yong Kim ◽  
Hong-Gyu Park ◽  
...  

2010 ◽  
Vol 157 (2) ◽  
pp. H214 ◽  
Author(s):  
S. J. Lim ◽  
Jae-Min Kim ◽  
Doyoung Kim ◽  
Soonju Kwon ◽  
Jin-Seong Park ◽  
...  

RSC Advances ◽  
2016 ◽  
Vol 6 (95) ◽  
pp. 92534-92540 ◽  
Author(s):  
Eom-Ji Kim ◽  
Won-Ho Lee ◽  
Sung-Min Yoon

We proposed a methodology for controlling the threshold voltage by adjusting the position of the Al dopant layer within an Al-doped-ZnO active channel of a thin film transistor.


RSC Advances ◽  
2015 ◽  
Vol 5 (29) ◽  
pp. 22712-22717 ◽  
Author(s):  
Soumyadeep Sinha ◽  
Devika Choudhury ◽  
Gopalan Rajaraman ◽  
Shaibal K. Sarkar

DFT study of the growth mechanism of atomic layer deposited Zn3N2 thin film applied as a channel layer of TFT.


Coatings ◽  
2021 ◽  
Vol 11 (8) ◽  
pp. 969
Author(s):  
Haiyang Xu ◽  
Xingwei Ding ◽  
Jie Qi ◽  
Xuyong Yang ◽  
Jianhua Zhang

In this work, Y2O3–Al2O3 dielectrics were prepared and used in ZnO thin film transistor as gate insulators. The Y2O3 film prepared by the sol–gel method has many surface defects, resulting in a high density of interface states with the active layer in TFT, which then leads to poor stability of the devices. We modified it by atomic layer deposition (ALD) technology that deposited a thin Al2O3 film on the surface of a Y2O3 dielectric layer, and finally fabricated a TFT device with ZnO as the active layer by ALD. The electrical performance and bias stability of the ZnO TFT with a Y2O3–Al2O3 laminated dielectric layer were greatly improved, the subthreshold swing was reduced from 147 to 88 mV/decade, the on/off-state current ratio was increased from 4.24 × 106 to 4.16 × 108, and the threshold voltage shift was reduced from 1.4 to 0.7 V after a 5-V gate was is applied for 800 s.


2016 ◽  
Vol 56 ◽  
pp. 324-328 ◽  
Author(s):  
Rongsheng Liu ◽  
Minfang Peng ◽  
Haiyan Zhang ◽  
Xun Wan ◽  
Meie Shen

Sign in / Sign up

Export Citation Format

Share Document