scholarly journals Recent Results on the Implementation of a Burst Error and Burst Erasure Channel Emulator Using an FPGA Architecture

2020 ◽  
Vol 16 (1) ◽  
pp. 19-29
Author(s):  
Caterina Travan ◽  
Francesca Vatta ◽  
Fulvio Babich
Keyword(s):  
Graphics Processing Unit ◽  
General Purpose ◽  
Processing Unit ◽  
Transmission Channel ◽  
Central Processing ◽  
Fpga Architecture ◽  
Burst Error ◽  
Field Programmable ◽  
Erasure Channel ◽  
Burst Erasure

The behaviour of a transmission channel may be simulated using the performance abilities of current generation multiprocessing hardware, namely, a multicore Central Processing Unit (CPU), a general purpose Graphics Processing Unit (GPU), or a Field Programmable Gate Array (FPGA). These were investigated by Cullinan et al. in a recent paper (published in 2012) where these three devices capabilities were compared to determine which device would be best suited towards which specific task. In particular, it was shown that, for the application which is objective of our work (i.e., for a transmission channel simulation), the FPGA is 26.67 times faster than the GPU and 10.76 times faster than the CPU. Motivated by these results, in this paper we propose and present a direct hardware emulation. In particular, a Cyclone II FPGA architecture is implemented to simulate a burst error channel behaviour, in which errors are clustered together, and a burst erasure channel behaviour, in which the erasures are clustered together. The results presented in the paper are valid for any FPGA architecture that may be considered for this scope.

scholarly journals Analysis of Fast Fourier Transformations algorithm for CUDA Architecture

2012 ◽  
Vol 53 ◽  
Author(s):  
Beatričė Andziulienė ◽  
Evaldas Žulkas ◽  
Audrius Kuprinavičius
Keyword(s):  
Graphics Processing Unit ◽  
General Purpose ◽  
Fast Fourier Transformation ◽  
Processing Unit ◽  
Data Allocation ◽  
Analysis Method ◽  
Central Processing ◽  
Execution Speed ◽  
Cuda Architecture ◽  
Graphics Processing

In this work Fast Fourier transformation algorithm for general purpose graphics processing unit processing (GPGPU) is discussed. Algorithm structure and individual stages performance were analysed. With performance analysis method algorithm distribution and data allocation possibilities were determined, depending on algorithm stages execution speed and algorithm structure. Ratio between CPU and GPU execution during Fast Fourier transform signal processing was determined using computer-generated data with frequency. When adopting CPU code for CUDA execution, it not becomes more complex, even if stream procesor parallelization and data transfering algorith stages are considered. But central processing unit serial execution).

scholarly journals Optimized Compression for Implementing Convolutional Neural Networks on FPGA

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 295 ◽  
Author(s):  
Min Zhang ◽  
Linpeng Li ◽  
Hai Wang ◽  
Yan Liu ◽  
Hongbo Qin ◽  
...  
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Short Term Memory ◽  
Graphics Processing Unit ◽  
Processing Unit ◽  
Central Processing ◽  
Pruning Strategy ◽  
Field Programmable ◽  
Storage Format ◽  
Evaluation Board

Field programmable gate array (FPGA) is widely considered as a promising platform for convolutional neural network (CNN) acceleration. However, the large numbers of parameters of CNNs cause heavy computing and memory burdens for FPGA-based CNN implementation. To solve this problem, this paper proposes an optimized compression strategy, and realizes an accelerator based on FPGA for CNNs. Firstly, a reversed-pruning strategy is proposed which reduces the number of parameters of AlexNet by a factor of 13× without accuracy loss on the ImageNet dataset. Peak-pruning is further introduced to achieve better compressibility. Moreover, quantization gives another 4× with negligible loss of accuracy. Secondly, an efficient storage technique, which aims for the reduction of the whole overhead cache of the convolutional layer and the fully connected layer, is presented respectively. Finally, the effectiveness of the proposed strategy is verified by an accelerator implemented on a Xilinx ZCU104 evaluation board. By improving existing pruning techniques and the storage format of sparse data, we significantly reduce the size of AlexNet by 28×, from 243 MB to 8.7 MB. In addition, the overall performance of our accelerator achieves 9.73 fps for the compressed AlexNet. Compared with the central processing unit (CPU) and graphics processing unit (GPU) platforms, our implementation achieves 182.3× and 1.1× improvements in latency and throughput, respectively, on the convolutional (CONV) layers of AlexNet, with an 822.0× and 15.8× improvement for energy efficiency, separately. This novel compression strategy provides a reference for other neural network applications, including CNNs, long short-term memory (LSTM), and recurrent neural networks (RNNs).

scholarly journals Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design

2017 ◽  
Vol 27 (03n04) ◽  
pp. 1750006 ◽  
Author(s):  
Farhad Merchant ◽  
Anupam Chattopadhyay ◽  
Soumyendu Raha ◽  
S. K. Nandy ◽  
Ranjani Narayan
Keyword(s):  
Linear Algebra ◽  
High Performance ◽  
Graphics Processing Unit ◽  
Building Blocks ◽  
General Purpose ◽  
Performance Tuning ◽  
Floating Point ◽  
Processing Unit ◽  
Field Programmable ◽  
The Impact

Basic Linear Algebra Subprograms (BLAS) and Linear Algebra Package (LAPACK) form basic building blocks for several High Performance Computing (HPC) applications and hence dictate performance of the HPC applications. Performance in such tuned packages is attained through tuning of several algorithmic and architectural parameters such as number of parallel operations in the Directed Acyclic Graph of the BLAS/LAPACK routines, sizes of the memories in the memory hierarchy of the underlying platform, bandwidth of the memory, and structure of the compute resources in the underlying platform. In this paper, we closely investigate the impact of the Floating Point Unit (FPU) micro-architecture for performance tuning of BLAS and LAPACK. We present theoretical analysis for pipeline depth of different floating point operations like multiplier, adder, square root, and divider followed by characterization of BLAS and LAPACK to determine several parameters required in the theoretical framework for deciding optimum pipeline depth of the floating operations. A simple design of a Processing Element (PE) is presented and shown that the PE outperforms the most recent custom realizations of BLAS and LAPACK by 1.1X to 1.5X in GFlops/W, and 1.9X to 2.1X in Gflops/mm2. Compared to multicore, General Purpose Graphics Processing Unit (GPGPU), Field Programmable Gate Array (FPGA), and ClearSpeed CSX700, performance improvement of 1.8-80x is reported in PE.

scholarly journals SatEC: A 5G Satellite Edge Computing Framework Based on Microservice Architecture

Sensors ◽  
2019 ◽  
Vol 19 (4) ◽  
pp. 831 ◽  
Author(s):  
Lei Yan ◽  
Suzhi Cao ◽  
Yongsheng Gong ◽  
Hao Han ◽  
Junyong Wei ◽  
...  
Keyword(s):  
Graphics Processing Unit ◽  
Edge Computing ◽  
Satellite Network ◽  
Processing Unit ◽  
Central Processing ◽  
5G Network ◽  
Field Programmable ◽  
High Bandwidth ◽  
Basic Services ◽  
Computing Framework

As outlined in the 3Gpp Release 16, 5G satellite access is important for 5G network development in the future. A terrestrial-satellite network integrated with 5G has the characteristics of low delay, high bandwidth, and ubiquitous coverage. A few researchers have proposed integrated schemes for such a network; however, these schemes do not consider the possibility of achieving optimization of the delay characteristic by changing the computing mode of the 5G satellite network. We propose a 5G satellite edge computing framework (5GsatEC), which aims to reduce delay and expand network coverage. This framework consists of embedded hardware platforms and edge computing microservices in satellites. To increase the flexibility of the framework in complex scenarios, we unify the resource management of the central processing unit (CPU), graphics processing unit (GPU), and field-programmable gate array (FPGA); we divide the services into three types: system services, basic services, and user services. In order to verify the performance of the framework, we carried out a series of experiments. The results show that 5GsatEC has a broader coverage than the ground 5G network. The results also show that 5GsatEC has lower delay, a lower packet loss rate, and lower bandwidth consumption than the 5G satellite network.

scholarly journals Fast Effective Deterministic Primality Test Using CUDA/GPGPU

2014 ◽  
Vol 12 (3) ◽  
pp. 3338-3346
Author(s):  
Abu Asaduzzaman ◽  
Anindya Maiti ◽  
Chok Meng Yip
Keyword(s):  
Computer Security ◽  
Graphics Processing Unit ◽  
Prime Numbers ◽  
Deterministic Algorithm ◽  
General Purpose ◽  
Processing Unit ◽  
Central Processing ◽  
Primality Test ◽  
Testing Algorithms ◽  
Graphics Processing

There are great interests in understanding the manner by which the prime numbers are distributed throughout the integers. Prime numbers are being used in secret codes for more than 60 years now. Computer security authorities use extremely large prime numbers when they devise cryptographs, like RSA (short for Rivest, Shamir, and Adleman) algorithm, for protecting vital information that is transmitted between computers. There are many primality testing algorithms including mathematical models and computer programs. However, they are very time consuming when the given number n is very big or n→∞. In this paper, we propose a novel parallel computing model based on a deterministic algorithm using central processing unit (CPU) / general-purpose graphics processing unit (GPGPU) systems, which determines whether an input number is prime or composite much faster. We develop and implement the proposed algorithm using a system with a 8-core CPU and a 448-core GPGPU. Experimental results indicate that upto 94.35x speedup can be achieved for 21-digit decimal numbers.

scholarly journals A TensorFlow Extension Framework for Optimized Generation of Hardware CNN Inference Engines

Technologies ◽  
2020 ◽  
Vol 8 (1) ◽  
pp. 6 ◽  
Author(s):  
Vasileios Leon ◽  
Spyridon Mouselinos ◽  
Konstantina Koliogeorgi ◽  
Sotirios Xydis ◽  
Dimitrios Soudris ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Graphics Processing Unit ◽  
Inference Engine ◽  
Efficient Solutions ◽  
Processing Unit ◽  
Central Processing ◽  
Inference Engines ◽  
Field Programmable ◽  
Hardware Description

The workloads of Convolutional Neural Networks (CNNs) exhibit a streaming nature that makes them attractive for reconfigurable architectures such as the Field-Programmable Gate Arrays (FPGAs), while their increased need for low-power and speed has established Application-Specific Integrated Circuit (ASIC)-based accelerators as alternative efficient solutions. During the last five years, the development of Hardware Description Language (HDL)-based CNN accelerators, either for FPGA or ASIC, has seen huge academic interest due to their high-performance and room for optimizations. Towards this direction, we propose a library-based framework, which extends TensorFlow, the well-established machine learning framework, and automatically generates high-throughput CNN inference engines for FPGAs and ASICs. The framework allows software developers to exploit the benefits of FPGA/ASIC acceleration without requiring any expertise on HDL development and low-level design. Moreover, it provides a set of optimization knobs concerning the model architecture and the inference engine generation, allowing the developer to tune the accelerator according to the requirements of the respective use case. Our framework is evaluated by optimizing the LeNet CNN model on the MNIST dataset, and implementing FPGA- and ASIC-based accelerators using the generated inference engine. The optimal FPGA-based accelerator on Zynq-7000 delivers 93% less memory footprint and 54% less Look-Up Table (LUT) utilization, and up to 10× speedup on the inference execution vs. different Graphics Processing Unit (GPU) and Central Processing Unit (CPU) implementations of the same model, in exchange for a negligible accuracy loss, i.e., 0.89%. For the same accuracy drop, the 45 nm standard-cell-based ASIC accelerator provides an implementation which operates at 520 MHz and occupies an area of 0.059 mm 2 , while the power consumption is ∼7.5 mW.

High-performance computer graphics technologies in engineering applications

2019 ◽  
Vol 16 (2) ◽  
pp. 304-308
Author(s):  
Chao Peng
Keyword(s):  
Computer Graphics ◽  
High Performance ◽  
Graphics Processing Unit ◽  
General Purpose ◽  
Processing Unit ◽  
Data Streaming ◽  
Engineering Applications ◽  
Content Type ◽  
Central Processing ◽  
Advantages And Disadvantages

Purpose The purpose of this paper is to investigate possibilities to adopt state-of-the-art computer graphics technologies for big data visualization in engineering applications. Toward this purpose, a conceptual heterogeneous system is proposed for graphical rendering, which is established with multiple central processing unit cores and multiple graphics processing unit GPUs. Design/methodology/approach The design of the system supports both general-purpose computation and graphics-related computation. Three processing components are discussed to fulfill the execution requirements in load balancing, data streaming and display. This design fully uses computational and memory resources and enhances the performance with the support of GPU-based parallelization. Findings The advantages and disadvantages of particular technical methods for each processing component are discussed. The possible ways to integrate them are analyzed. Originality/value This work has contributions of using computer graphics technologies in engineering applications.

scholarly journals Numerical simulation of flattened heat pipe with double heat sources for CPU and GPU cooling application in laptop computers

2020 ◽  
Author(s):  
Wisoot Sanhan ◽  
Kambiz Vafai ◽  
Niti Kammuang-Lue ◽  
Pradit Terdtoon ◽  
Phrut Sakulchangsatjatai
Keyword(s):  
Experimental Data ◽  
Heat Pipe ◽  
Graphics Processing Unit ◽  
Processing Unit ◽  
Heat Sources ◽  
Final Thickness ◽  
Laptop Computers ◽  
Central Processing ◽  
Graphics Processing ◽  
Good Agreement

Abstract An investigation of the effect of the thermal performance of the flattened heat pipe on its double heat sources acting as central processing unit and graphics processing unit in laptop computers is presented in this work. A finite element method is used for predicting the flattening effect of the heat pipe. The cylindrical heat pipe with a diameter of 6 mm and the total length of 200 mm is flattened into three final thicknesses of 2, 3, and 4 mm. The heat pipe is placed under a horizontal configuration and heated with heater 1 and heater 2, 40 W in combination. The numerical model shows good agreement compared with the experimental data with the standard deviation of 1.85%. The results also show that flattening the cylindrical heat pipe to 66.7 and 41.7% of its original diameter could reduce its normalized thermal resistance by 5.2%. The optimized final thickness or the best design final thickness for the heat pipe is found to be 2.5 mm.

scholarly journals A Parallel-Computing Approach for Vector Road-Network Matching Using GPU Architecture

2018 ◽  
Vol 7 (12) ◽  
pp. 472 ◽  
Author(s):  
Bo Wan ◽  
Lin Yang ◽  
Shunping Zhou ◽  
Run Wang ◽  
Dezhi Wang ◽  
...  
Keyword(s):  
Road Network ◽  
Large Scale ◽  
Graphics Processing Unit ◽  
Road Networks ◽  
Processing Unit ◽  
Data Partition ◽  
Matching Method ◽  
The Road ◽  
Central Processing ◽  
Relaxation Matching

The road-network matching method is an effective tool for map integration, fusion, and update. Due to the complexity of road networks in the real world, matching methods often contain a series of complicated processes to identify homonymous roads and deal with their intricate relationship. However, traditional road-network matching algorithms, which are mainly central processing unit (CPU)-based approaches, may have performance bottleneck problems when facing big data. We developed a particle-swarm optimization (PSO)-based parallel road-network matching method on graphics-processing unit (GPU). Based on the characteristics of the two main stages (similarity computation and matching-relationship identification), data-partition and task-partition strategies were utilized, respectively, to fully use GPU threads. Experiments were conducted on datasets with 14 different scales. Results indicate that the parallel PSO-based matching algorithm (PSOM) could correctly identify most matching relationships with an average accuracy of 84.44%, which was at the same level as the accuracy of a benchmark—the probability-relaxation-matching (PRM) method. The PSOM approach significantly reduced the road-network matching time in dealing with large amounts of data in comparison with the PRM method. This paper provides a common parallel algorithm framework for road-network matching algorithms and contributes to integration and update of large-scale road-networks.

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