SIMULATION OF AN ADARTIVE FILTER BASED ON THE RECURSIVE LEAST SQUARES METHOD

Modern electronics systems are high-speed, compact and require the use of energy-efficient digital electronics devices (DED’s) such as microcontrollers, programmable logic integrated circuits (FPGA’s), digital signal processors. Application of the DED’s is a hardware implementation of high - performance digital signal processing (DSP) algorithms based on the target architecture of the electronic device. In order to accellarate of the design process in the direct hardware implementation of DSP algorithms, simulation models are created to enable optimizing the design process at the stage of a creation of the programming part for FPGA. The paper presents the results of a study of the adaptive filter (AF) model based on the recursive least squares method (RLS). According to the analysis of time and frequency parameters of the AF model has been conducted during simulation it was found that the qualitative filtering process starting from the 24th order and further increasing the AF order does not significantly improve signal filtering, but only increases the required hardware resources. In process of the verification of the proposed simulation model, the AF-based noise reduction system has been modeled and the THD level of 7.103 % was obtained for the built-in AF unit, which is more than one and a half times higher than the proposed AF unit 4.323 %, which confirmed the efficiency of the developed AF unit. Thus, during the study, the optimal order of AF has been determined, which will allow more efficient use of FPGA resources during the hardware implementation of AF. In accordance with the results of the study, the correctness and efficiency of the created hardware-oriented simulation model has been proved, as well as the hardware-oriented structure of the adaptive RLS filter for future implementation on FPGA nas been shown.