Interconnect and Gate Level Delayering Techniques for Cu/Low k Technology Failure Analysis

2003 ◽  
Author(s):  
Huixian Wu ◽  
James Cargo ◽  
Barry Dutt ◽  
Tony Bucha ◽  
Joe Serpiello
Keyword(s):  
Failure Analysis ◽  
Chemical Mechanical Polishing ◽  
Failure Modes ◽  
Reactive Ion Etching ◽  
Mechanical Polishing ◽  
Front Side ◽  
Ion Etching ◽  
Low K

Abstract In this paper, Failure Analysis (FA) challenges, reliability issues, and new failure modes for copper technology will be presented. Deprocessing techniques for copper technology have been developed and will be discussed. Front side and backside FA deprocessing techniques for copper layers and low k inter-level dielectric (ILD) layers including: reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and a combination of these techniques will be discussed. In addition, novel gate level deprocessing techniques will be presented.

Grinding and chemical mechanical polishing process for micropore x-ray optics fabricated with deep reactive ion etching

2019 ◽  
Vol 58 (19) ◽  
pp. 5240 ◽  
Author(s):  
Aoto Fukushima ◽  
Maiko Fujitani ◽  
Kumi Ishikawa ◽  
Masaki Numazawa ◽  
Daiki Ishi ◽  
...  
Keyword(s):  
Chemical Mechanical Polishing ◽  
Reactive Ion Etching ◽  
Mechanical Polishing ◽  
Polishing Process ◽  
Ion Etching ◽  
Ray Optics ◽  
Deep Reactive Ion Etching ◽  
X Ray ◽  
Chemical Mechanical Polishing Process

Chemical Mechanical Polishing and a Succedent Reactive Ion Etching Processing of Sapphire Wafer

2007 ◽  
Vol 154 (3) ◽  
pp. H166 ◽  
Author(s):  
Liangyong Wang ◽  
Kailiang Zhang ◽  
Zhitang Song ◽  
Songlin Feng
Keyword(s):  
Chemical Mechanical Polishing ◽  
Reactive Ion Etching ◽  
Mechanical Polishing ◽  
Ion Etching ◽  
Sapphire Wafer

Failure Modes, Reliability Analysis and Case Studies on the Integration of Copper and Low-K Technology

2004 ◽  
Author(s):  
Huixian Wu ◽  
James Cargo ◽  
Huixian Wu ◽  
Marvin White
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Copper Interconnects ◽  
Wet Chemical ◽  
Low K ◽  
Section Analysis

Abstract The integration of copper interconnects and low-K dielectrics will present novel failure modes and reliability issues to failure analysts. This paper discusses failure modes related to Cu/low-K technology. Here, physical failure analysis (FA) techniques including deprocessing and cross-section analysis have been developed. The deprocessing techniques include wet chemical etching, reactive ion etching, chemical mechanical polishing and a combination of these techniques. Case studies on different failure modes related to Cu/low k technology are discussed: copper voiding, copper extrusion; electromigration stress failure; dielectric cracks; delamination-interface adhesion; and FA on circuit-under-pad. For the cross-section analysis of copper/low-K samples, focused ion beam techniques have been developed. Scanning electron microscopy, EDX, and TEM analytical analysis have been used for failure analysis for Cu/low-K technology. Various failure modes and reliability issues have also been addressed.

A Model for Optimizing Material Removal Rate in Low-Pressure CMP: Effects of Pad Porosity and Abrasive Concentration

2008 ◽  
Author(s):  
Dinc¸er Bozkaya ◽  
Sinan Mu¨ftu¨
Keyword(s):  
Material Removal Rate ◽  
Chemical Mechanical Polishing ◽  
Material Removal ◽  
Removal Rate ◽  
Applied Pressure ◽  
Low Pressure ◽  
Mechanical Polishing ◽  
Low K

The necessity to planarize ultra low-k (ULK) dielectrics [1], and the desire to reduce polishing defects leads to use of lower polishing pressures in chemical mechanical polishing (CMP). However, lowering the applied pressure also decreases the material removal rate (MRR), which causes the polishing time for each wafer to increase. The goal of this work is to investigate effects of pad porosity and abrasive concentration on the MRR.

Automated Sample Preparation of Low-k Dielectrics for FESEM

2005 ◽  
Author(s):  
R. R. Cerchiara ◽  
H. A. Cook ◽  
P. E. Fischione ◽  
J. J. Gronsky ◽  
J. M. Matesa ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Ion Beam ◽  
Reactive Ion Etching ◽  
Copper Interconnects ◽  
Plasma Cleaning ◽  
Ion Etching ◽  
Ion Beam Etching ◽  
Automated Sample Preparation ◽  
Microelectronic Materials ◽  
Low K

Abstract The SiLK resins, composed of aromatic hydrocarbons, are a family of highly cross-linked thermoset polymers with isotropic dielectric properties. Patterning of SiLK for high aspect ratio copper interconnects has depended on reactive ion etching with oxygen/nitrogen gas mixtures. Reactive ion etching is therefore also accomplished with reducing plasmas such as nitrogen/hydrogen. An additional plasma cleaning step can be inserted after the reactive ion etching (RIE) step, so that any residual contamination is removed prior to imaging or final sputter coating. Automated sample preparation of microelectronic materials containing high and low-k dielectrics for FESEM is accomplished in this article by combining these techniques: plasma cleaning, ion beam etching, and reactive ion etching. A single RIE chemistry was effective in etching both dielectrics as well as delineating the other phases present.

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