Failure Modes, Reliability Analysis and Case Studies on the Integration of Copper and Low-K Technology

2004 ◽  
Author(s):  
Huixian Wu ◽  
James Cargo ◽  
Huixian Wu ◽  
Marvin White
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Copper Interconnects ◽  
Wet Chemical ◽  
Low K ◽  
Section Analysis

Abstract The integration of copper interconnects and low-K dielectrics will present novel failure modes and reliability issues to failure analysts. This paper discusses failure modes related to Cu/low-K technology. Here, physical failure analysis (FA) techniques including deprocessing and cross-section analysis have been developed. The deprocessing techniques include wet chemical etching, reactive ion etching, chemical mechanical polishing and a combination of these techniques. Case studies on different failure modes related to Cu/low k technology are discussed: copper voiding, copper extrusion; electromigration stress failure; dielectric cracks; delamination-interface adhesion; and FA on circuit-under-pad. For the cross-section analysis of copper/low-K samples, focused ion beam techniques have been developed. Scanning electron microscopy, EDX, and TEM analytical analysis have been used for failure analysis for Cu/low-K technology. Various failure modes and reliability issues have also been addressed.

Focused Ion Beam Analysis of Low-K Dielectrics

2000 ◽  
Author(s):  
H. J. Bender ◽  
R. A. Donaton
Keyword(s):  
Electron Microscope ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Single Step ◽  
Specimen Preparation ◽  
Transmission Electron ◽  
Beam Analysis ◽  
Low K ◽  
Scanning Electron

Abstract The characteristics of an organic low-k dielectric during investigation by focused ion beam (FIB) are discussed for the different FIB application modes: cross-section imaging, specimen preparation for transmission electron microscopy, and via milling for device modification. It is shown that the material is more stable under the ion beam than under the electron beam in the scanning electron microscope (SEM) or in the transmission electron microscope (TEM). The milling of the material by H2O vapor assistance is strongly enhanced. Also by applying XeF2 etching an enhanced milling rate can be obtained so that both the polymer layer and the intermediate oxides can be etched in a single step.

Failure Analysis Strategies for Multistacked Memory Devices with TSV Interconnects

2015 ◽  
Author(s):  
Frank Altmann ◽  
Christian Grosse ◽  
Falk Naumann ◽  
Jens Beyersdorfer ◽  
Tony Veches
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Memory Devices ◽  
Metallographic Cross Section ◽  
Electron Beam Induced Current ◽  
Thermal Simulations ◽  
Lock In ◽  
Non Destructive

Abstract In this paper we will demonstrate new approaches for failure analysis of memory devices with multiple stacked dies and TSV interconnects. Therefore, TSV specific failure modes are studied on daisy chain test samples. Two analysis flows for defect localization implementing Electron Beam Induced Current (EBAC) imaging and Lock-in-Thermography (LIT) as well as adapted Focused Ion Beam (FIB) preparation and defect characterization by electron microscopy will be discussed. The most challenging failure mode is an electrical short at the TSV sidewall isolation with sub-micrometer dimensions. It is shown that the leakage path to a certain TSV within the stack can firstly be located by applying LIT to a metallographic cross section and secondly pinpointing by FIB/SEM cross-sectioning. In order to evaluate the potential of non-destructive determination of the lateral defect position, as well as the defect depth from only one LIT measurement, 2D thermal simulations of TSV stacks with artificial leakages are performed calculating the phase shift values per die level.

Advanced sub 0.13µm Cu Devices – Failure Analysis and Circuit Edit With Improved FIB Chemical Processes and Beam Characteristics

2002 ◽  
Author(s):  
J. David Casey ◽  
Thomas J. Gannon ◽  
Alex Krechmer ◽  
David Monforte ◽  
Nicholas Antoniou ◽  
...  
Keyword(s):  
Failure Analysis ◽  
High Speed ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Chemical Processes ◽  
Design Verification ◽  
End Point Detection ◽  
On Chip ◽  
Point Detection ◽  
Low K

Abstract Advances in FIB (focused ion beam) chemical processes and in the Ga (gallium) beam profile are discussed; these advances are necessary for the successful failure analysis, circuit edit and design verification of advanced, sub-0.13µm Cu devices. Included in this article are: a novel FIB method (CopperRx) for smoothly milling thick, large grained Cu lines; H2O and O2 processes for cleanly cutting thin, smaller grained Cu lines, thereby forming electrically open interconnects; a XeF2 GAE (gas assisted etching) process for etching low k, CVD dielectrics such as F and C doped SiO2; H2O and XeF2 GAE processes for etching low k, spin-on, organic dielectrics such as SiLK; a recently developed recipe for the deposition of SiO2 based material with intermediate resistivity (106 µohm·cm) which is useful in the design verification of frequency sensitive, high speed analog and SOC (system on chip) circuits; an improved, more Gaussian Ga beam with less current density in the beam tails (VisION column) which provides higher resolution, real time images needed for end-point detection on sub 0.13µm features during milling.

scholarly journals Practical Methodologies in Restoring Initial Failure Mode and Backside Focused Ion Beam Cross-Section for Defect Visualization

2021 ◽  
Author(s):  
Alvina Jean Tampos ◽  
Karl Villareal
Keyword(s):  
Failure Mode ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Image Sensor ◽  
Fault Isolation ◽  
Third Party ◽  
Oxide Semiconductor ◽  
Back Side

Abstract Complementary Metal-Oxide Semiconductor (CMOS) Image Sensors are gaining popularity most especially in Automotive Safety and Advanced Driver-Assistance Systems (ADAS) applications. Customer application modules involve oftentimes a third party supplier. When failures involve interaction between an image sensor die and the customer's module, the Failure Analyst has to know the exact failure mechanism to pinpoint whether root cause is in the die fabrication (fab) or packaging assembly (third party supplier). Challenges can befall the analyst: failure modes can recover which renders the unit functional and laboratories most often do not have complete sophisticated analytical laboratory equipment for electrical testing, fault isolation and sample preparation. In this paper, a case study of a CMOS Image Sensor is presented wherein the failure mode recovered which was restored and how the structural limitations were overcome for fault isolation on both front- and back-side. A modified process flow was performed to visualize the defect through backside Focused Ion Beam (FIB) cross-section.

Failure Analysis of a Transistor Lead

2000 ◽  
Author(s):  
Yasushi Deguchi ◽  
Sumio Matsuda ◽  
Jiro Aoki ◽  
Takashi Tamura ◽  
Yasunobu Iwai ◽  
...  
Keyword(s):  
Sulfuric Acid ◽  
Low Power ◽  
Failure Analysis ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Protective Coatings ◽  
Ion Beam ◽  
Worst Case ◽  
Dissolved Ions ◽  
Plating Layer

Abstract We investigated the cause of the whisker/discoloration which were found in the transistor lead of stocks (package type TO-18, low power use). In process of the investigation, we estimate two corrosion models that the first model is the remnant of sulfuric acid in cracks of the nickel-phosphorus plating layer in the transistor lead, the second model is the out-gassing or the dissolved ions from the stock container and conductive mat. As the results of the investigation which includes analyses of the whisker/discoloration cross section made by FIB (Focused Ion Beam), a reproductive experiment and so on, the whisker/discoloration were the corrosion reacted between the solder (Pb-Sn) on the transistor lead and SO42- ions of the stock container. We estimate that the new corrosion will not occur and grow in mounted devices because of rejecting the source of corrosion (stock containers). Further, in the worst case of the corrosion occurrence, protective coatings were applied to the mounted transistor lead, as the measure against falling away from the transistor lead.

Failure Analysis of DRAM Storage Node Trench Capacitors for 0.35-Micron and Follow-On Technologies Using the Focused Ion Beam for Electrical and Physical Analysis

1996 ◽  
Author(s):  
G. Benstetter ◽  
G. Bomberger ◽  
P. Coutu ◽  
R. Danyew ◽  
R. Douse
Keyword(s):  
High Resolution ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Substrate Material ◽  
Mechanical Polishing ◽  
Physical Analysis ◽  
Storage Node ◽  
Wet Chemical ◽  
Voltage Contrast

Abstract Reducing the cell size of DRAMs in 0.35 micron and follow-on technologies requires failure analysis techniques that can analyze single storage node trench capacitors on both test sites and actual product. A combination of electrical microprobing, probeless voltage contrast and physical delayering procedures, all based on focused- ion-beam (FIB) techniques, are described. Because of precise fail localization, high resolution scanning electron microscope (SEM) imaging enables the distinction between process defects and intrinsic breakdowns of node dielectric defects. Isolated storage cells can be electrically characterized by depositing small probe pads, using FIB for contact hole milling and probe-pad deposition. To localize trench capacitors with a leakage path to the surrounding substrate, the trenches are isolated by mechanical polishing and probeless voltage contrast in the FIB tool. Failing trench capacitors can be marked in the FIB tool. Physical isolation of leaking trench capacitors can be achieved by recessing the adjacent trench capacitors, with the FIB used for milling and a subsequent wet chemical removal added for the remaining substrate material. Alternatively, trench capacitors can be inspected from the backside when stabilized by a quartz deposition on top, followed by mechanical polishing from the side and a wet chemical etching of the remaining substrate material. In both cases, the dielectric of the node trench capacitors can be inspected by high resolution SEMs and the defect areas precisely analyzed.

Study on BEOL Failures in a Chip by Shear Tests of Copper Pillar Bumps

2019 ◽  
Vol 141 (1) ◽  
Author(s):  
Lei Wang ◽  
Jun Wang ◽  
Fei Xiao
Keyword(s):  
Shear Test ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Maximum Shear Stress ◽  
Dielectric Materials ◽  
Electrical Performance ◽  
Element Analysis ◽  
Shear Speed ◽  
Low K

A chip with 40 nm technology node and beyond generally incorporates low-k/ultra-low-k (LK/ULK) dielectric materials and copper traces in the back end of line (BEOL) to improve its electrical performance. Owing to the fragile low-k/ultra-low-k materials, the BEOL becomes vulnerable to external loads. When a copper pillar bump (CPB) above the BEOL sustains a shear force due to thermal mismatch between the components, failures occur in the microstructures of BEOL, especially in low-k materials. We fabricated CPBs on the chips and investigated fractures in the BEOL by a shear test approach. The shear speed and shear height are varied to examine their effects. The tested samples were analyzed via focused ion beam (FIB) and scanning electron microscope (SEM) to reveal the microstructures degradation or breaks in the BEOL, and they are classified into three kinds of failure modes. Assisted by a finite element analysis (FEA), the failure mechanism was explained and associated with the failure modes. The studies showed that the shear speed has a little influence on the maximum shear stress, but the increase of shear height leads to more fractures in the low-k materials. It indicated that decreasing the height of CPBs is helpful for reducing destruction risk of the BEOL under the thermomechanical loads. Based on a parametric study for shearing test simulation of a single CPB, the modulus and thickness of polyimide (PI) were found a larger impact on the stresses in the low-k material layer, but the modulus of low-k materials has a smaller effect on the stress. Generally, the shear test of a CPB can help to evaluate the integrity of BEOL in a chip.

Imaging Thin Films of Nanoporous Low-k Dielectrics: Comparison between Ultramicrotomy and Focused Ion Beam Preparations for Transmission Electron Microscopy

2005 ◽  
Vol 12 (2) ◽  
pp. 156-159 ◽  
Author(s):  
Leslie E. Thompson ◽  
Philip M. Rice ◽  
Eugene Delenia ◽  
Victor Y. Lee ◽  
Phillip J. Brock ◽  
...  
Keyword(s):  
Thin Films ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Preparation Method ◽  
Ion Beam ◽  
Specimen Preparation ◽  
Ion Milling ◽  
Transmission Electron ◽  
Low K ◽  
Diamond Knife

Ultramicrotomy, the technique of cutting nanometers-thin slices of material using a diamond knife, was applied to prepare transmission electron microscope (TEM) specimens of nanoporous poly(methylsilsesquioxane) (PMSSQ) thin films. This technique was compared to focused ion beam (FIB) cross-section preparation to address possible artifacts resulting from deformation of nanoporous microstructure during the sample preparation. It was found that ultramicrotomy is a successful TEM specimen preparation method for nanoporous PMSSQ thin films when combined with low-energy ion milling as a final step. A thick, sacrificial carbon coating was identified as a method of reducing defects from the FIB process which included film shrinkage and pore deformation.

Automated Diagonal Slice and View Solution for 3D Device Structure Analysis

2018 ◽  
Author(s):  
Sang Hoon Lee ◽  
Jeff Blackwood ◽  
Stacey Stone ◽  
Michael Schmidt ◽  
Mark Williamson ◽  
...  
Keyword(s):  
Cross Section ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Image Data ◽  
Planar Surface ◽  
Device Structure ◽  
Cross Sectional ◽  
Device Structures ◽  
The Cross ◽  
Planar Analysis

Abstract The cross-sectional and planar analysis of current generation 3D device structures can be analyzed using a single Focused Ion Beam (FIB) mill. This is achieved using a diagonal milling technique that exposes a multilayer planar surface as well as the cross-section. this provides image data allowing for an efficient method to monitor the fabrication process and find device design errors. This process saves tremendous sample-to-data time, decreasing it from days to hours while still providing precise defect and structure data.

Electrical Characterization of Different Failure Modes in Sub-100 nm Devices Using Nanoprobing Technique

2009 ◽  
Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
J. Sudijono ◽  
P.K. Tan ◽  
H. Tan ◽  
...  
Keyword(s):  
Electron Microscope ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Nickel Silicide ◽  
Fault Isolation ◽  
Technology Nodes ◽  
Scanning Electron

Abstract The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.

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