Obtaining Low Contact Resistance for Physical Sub-Micron Fault Isolation

The continued application and extension of Moore’s is Law driving semiconductor development into the deep submicron range. 90nm processes are pushing the limits of current technology, and announcements for 65nm and even smaller process developments are common place. Inspection and deprocessing tools are pacing these developments with moderate levels of success [1]. Fault isolation, however, and particularly physical fault isolation at these levels represents perhaps the most daunting of challenges facing today’s semiconductor companies. Possibly the most important failure analysis step, physical fault isolation of sub-micron devices, is growing increasingly more challenging. Traditional probe stations find limitation below 500nm feature sizes. Recent approaches to probing smaller geometries, such as AFM (Atomic Force Microscopy), have come up short in flexibility and applicability. Deposition of FIB pads can change circuit characteristics, is costly and time consuming, and is becoming increasingly more difficult as proximities decrease. Successful probing of structures smaller than 300nm require careful consideration to reduce and stabilize contact resistance (RC). A NANO-100TM probe station with SEM optics was used to analyze characteristics of, and the process needed to obtain stable, low RC for physical submicron fault isolation. Main discussion topics include probe tip oxidation, test timing and sample preparation. Probe tip selection, probe scrub, and attack angle are also mentioned. Recommendations and findings are presented for immediate application. It is shown that if the proper steps and considerations are made, stable RC of less than 10V is possible when probing sub-micron devices.