Failure Analysis and Process Verification of High-Density Copper ICs Used in Multichip Modules

2017 ◽  
Author(s):  
Jeremy A. Walraven ◽  
Mark W. Jenkins ◽  
Tuyet N. Simmons ◽  
James E. Levy ◽  
Sara E. Jensen ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Root Cause Analysis ◽  
Multichip Modules ◽  
Cause Analysis ◽  
Process Verification ◽  
Root Cause ◽  
Corrective Actions ◽  
Silicon Vias ◽  
Metal Layers

Abstract Manufacturing of integrated circuits (ICs) using a split foundry process expands design space in IC fabrication by employing unique capabilities of multiple foundries and provides added security for IC designers [1]. Defect localization and root cause analysis is critical to failure identification and implementation of corrective actions. In addition to split-foundry fabrication, the device addressed in this publication is comprised of 8 metal layers, aluminum test pads, and tungsten thru-silicon vias (TSVs) making the circuit area > 68% metal. This manuscript addresses the failure analysis efforts involved in root cause analysis, failure analysis findings, and the corrective actions implemented to eliminate these failure mechanisms from occurring in future product.

Wire-Wound Resistor Investigation—A Case Study

2016 ◽  
Author(s):  
Jason Wheeler ◽  
John Wolfgong
Keyword(s):  
Failure Analysis ◽  
Root Cause Analysis ◽  
Interesting Case ◽  
Cause Analysis ◽  
Root Cause ◽  
Resistive Element ◽  
Primary Driver ◽  
Mission Critical ◽  
Corrective Actions

Abstract The focus of this paper is to present an interesting case study involving Vishay wire-wound (WSC model) resistor failures, which affected a significant number of production and fielded assemblies. The failures were considered “mission critical”, which was the primary driver necessitating root cause analysis. A disciplined approach to the failure analysis effort was established, which resulted in root cause determination and the generation of appropriate corrective actions. This paper will highlight a non-conventional decapsulation method used to preserve the integrity of the fragile resistive element and a “lucky break” that was instrumental in linking the supplier’s actions to the failures.

Root Cause Analysis Techniques Using Picosecond Time Resolved LADA

2014 ◽  
Author(s):  
Dan Bodoh ◽  
Kent Erington ◽  
Kris Dickson ◽  
George Lange ◽  
Carey Wu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Picosecond Laser ◽  
Root Cause Analysis ◽  
Fault Isolation ◽  
Time Resolved ◽  
Cause Analysis ◽  
Root Cause ◽  
Design And Manufacturing ◽  
Multiple Interactions ◽  
Established Technique

Abstract Laser-assisted device alteration (LADA) is an established technique used to identify critical speed paths in integrated circuits. LADA can reveal the physical location of a speed path, but not the timing of the speed path. This paper describes the root cause analysis benefits of 1064nm time resolved LADA (TR-LADA) with a picosecond laser. It shows several examples of how picosecond TR-LADA has complemented the existing fault isolation toolset and has allowed for quicker resolution of design and manufacturing issues. The paper explains how TR-LADA increases the LADA localization resolution by eliminating the well interaction, provides the timing of the event detected by LADA, indicates the propagation direction of the critical signals detected by LADA, allows the analyst to infer the logic values of the critical signals, and separates multiple interactions occurring at the same site for better understanding of the critical signals.

Root Cause Analysis for Pin Leakage

2016 ◽  
Author(s):  
Zhigang Song ◽  
Jochonia Nxumalo ◽  
Manuel Villalobos ◽  
Sweta Pendyala
Keyword(s):  
Failure Analysis ◽  
Root Cause Analysis ◽  
Advanced Technology ◽  
Process Step ◽  
Cause Analysis ◽  
Hard Mask ◽  
Technology Node ◽  
Root Cause ◽  
Tools And Techniques

Abstract Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

Tri-Directional TEM Failure Analysis on Sample Prepared by In-Situ Lift-Out FIB and Flipstage

2014 ◽  
Author(s):  
Jie Zhu ◽  
An Yan Du ◽  
Bing Hai Liu ◽  
Eddie Er ◽  
Si Ping Zhao ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Cross Section ◽  
Root Cause Analysis ◽  
Wafer Surface ◽  
Tem Analysis ◽  
Cause Analysis ◽  
Root Cause

Abstract In this paper, we report an advanced sample preparation methodology using in-situ lift-out FIB and Flipstage for tridirectional TEM failure analysis. A planar-view and two cross-section TEM samples were prepared from the same target. Firstly, a planar-view lamellar parallel to the wafer surface was prepared using in-situ lift-out FIB milling. Upon TEM analysis, the planar sample was further milled in the along-gate and cross-gate directions separately. Eventually, a pillar-like sample containing a single transistor gate was obtained. Using this technique, we are able to analyze the defect from three perpendicular directions and obtain more information on the defect for failure root-cause analysis. A MOSFETs case study is described to demonstrate the procedure and advantages of this technique.

Challenges of System Level Failure Analysis of Electronics in the Automotive Industry

2017 ◽  
Author(s):  
Bence Hevesi
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Automotive Industry ◽  
Root Cause Analysis ◽  
Fault Isolation ◽  
System Level ◽  
Cause Analysis ◽  
Root Cause ◽  
Analysis Workflow

Abstract In this paper, different failure analysis (FA) workflows are showed which combines different FA approaches for fast and efficient fault isolation and root cause analysis in system level products. Two case studies will be presented to show the importance of a well-adjusted failure analysis workflow.

Missing Metal Pillar Failure Analysis-A Plug Technology Issue

2002 ◽  
Author(s):  
Dat Nguyen ◽  
Tim Campbell ◽  
Steven Whitlock ◽  
Ankineedu Velaga
Keyword(s):  
Failure Analysis ◽  
Chemical Mechanical Polishing ◽  
Significant Contribution ◽  
Process Engineering ◽  
Metal Line ◽  
Cause Analysis ◽  
Yield Analysis ◽  
Root Cause ◽  
Engineering Integration ◽  
Metal Layers

Abstract Smaller technologies and increasing chip functionality has resulted in tightly packed devices and more stacked metal layers. For technologies between 0.25µm and 0.14 µm, stacking packed metal layers required the combination of Tungsten plugs as interconnection and the utilization of Chemical Mechanical Polishing (CMP). “Pillar”, however, is a small metal line, which allows interlevel connections between Tungsten plugs. The size and shape of the pillar can be a yield limiting issue. The process of identification and resolution of the missing metal pillar included yield analysis, electrical and physical failure analysis, root cause analysis and the engineering coordination of photo engineering, etch process engineering, CMP engineering, integration engineering, and inline inspection. Resolving the missing pillar issue has proven to have significant contribution to yield.

Copper Bond Over Active Circuit (BOAC) and Copper Over Anything (COA) Failure Analysis

2003 ◽  
Author(s):  
Dat Nguyen ◽  
Bob Davis ◽  
Corey Lewis
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Circuit Boards ◽  
Electronic Industry ◽  
Cause Analysis ◽  
Defect Identification ◽  
Root Cause ◽  
Active Circuit ◽  
Selective Analysis

Abstract In today's electronic industry of shrinking circuit boards and shrinking semiconductor integrated circuits (IC), semiconductor companies have to be creative in providing devices with more circuitry on less silicon. Copper Bond over Active Circuit (BOAC)/Copper over Anything (COA) processes allow routing and bonding to thick top level metallization on the LinBiCMOS technology node. This paper discusses failure analysis (FA) techniques and approaches on un-passivated BOAC, and explains a generic BOAC/COA process. The approach to FA of BOAC involves package inspection-non intrusive analysis, decapsulation, die inspection, and defect identification/root cause analysis. Case studies are presented to explain the specific FA steps. Fault isolation involving BOAC requires the strategic removal of copper traces and selective analysis of the failed circuitry. Liquid crystal and micro-probing have been used effectively in failure isolation.

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