Low Power VLSI Design Techniques - The Current State

Jo Dale Carothers; Radjakichenin Radjassamy

doi:10.3233/ica-1998-5206

Low Power VLSI Design Techniques - The Current State

Integrated Computer-Aided Engineering ◽

10.3233/ica-1998-5206 ◽

1998 ◽

Vol 5 (2) ◽

pp. 153-176

Author(s):

Jo Dale Carothers ◽

Radjakichenin Radjassamy

Keyword(s):

Low Power ◽

Vlsi Design ◽

Current State ◽

Low Power Vlsi Design ◽

Design Techniques

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Stacked keeper with body bias: A new approach to reduce leakage power for low power VLSI design

2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies ◽

10.1109/icaccct.2014.7019482 ◽

2014 ◽

Cited By ~ 3

Author(s):

K. N. Bhargav ◽

A. Suresh ◽

Gaurav Saini

Keyword(s):

Low Power ◽

Vlsi Design ◽

Leakage Power ◽

New Approach ◽

Low Power Vlsi Design ◽

Body Bias

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VLSI design techniques for low power MAC unit: A review

10.1063/5.0057909 ◽

2021 ◽

Author(s):

Ajay Kumar Sahu ◽

Rashmi Samanth ◽

Tanya Mendez ◽

Subramanya G. Nayak ◽

K. Vishnumurthy Kedlaya

Keyword(s):

Low Power ◽

Vlsi Design ◽

Design Techniques

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Low-Power VLSI Design: An Overview

Low-Power Digital VLSI Design ◽

10.1007/978-1-4615-2355-0_1 ◽

1995 ◽

pp. 1-12

Author(s):

Abdellatif Bellaouar ◽

Mohamed I. Elmasry

Keyword(s):

Low Power ◽

Vlsi Design ◽

Low Power Vlsi Design

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Low-power VLSI design of arithmetic and logic circuits using the multiple-threshold CMOS technique

Smart Computing ◽

10.1201/9781003167488-78 ◽

2021 ◽

pp. 624-632

Author(s):

Prachi Kataria ◽

Anuwarti Rai ◽

Aanchal Singh ◽

Ashwin Anand ◽

Raman Kapoor ◽

...

Keyword(s):

Low Power ◽

Vlsi Design ◽

Logic Circuits ◽

Multiple Threshold ◽

Low Power Vlsi Design

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Low Power VLSI Design and Technology

10.1142/2984 ◽

1996 ◽

Cited By ~ 2

Author(s):

G K Yeap ◽

F N Najm

Keyword(s):

Low Power ◽

Vlsi Design ◽

Design And Technology ◽

Low Power Vlsi Design

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Trends in Low-Power VLSI Design

The Electrical Engineering Handbook ◽

10.1016/b978-012170960-0/50022-0 ◽

2005 ◽

pp. 263-280 ◽

Cited By ~ 3

Author(s):

Tarek Darwish ◽

Magdy Bayoumi

Keyword(s):

Low Power ◽

Vlsi Design ◽

Low Power Vlsi Design

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Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design

ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581) ◽

10.1145/383082.383156 ◽

2001 ◽

Cited By ~ 4

Author(s):

W. Chen ◽

W. Hwang ◽

P. Kudva ◽

G. Gristede ◽

S. Kosonocky ◽

...

Keyword(s):

Low Power ◽

Vlsi Design ◽

Low Power Vlsi Design

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A new leakage reduction method for ultra low power VLSI design for portable devices

2012 2nd International Conference on Power, Control and Embedded Systems ◽

10.1109/icpces.2012.6508074 ◽

2012 ◽

Cited By ~ 4

Author(s):

Asif Jahangir Chowdhury ◽

Md. Shahriar Rizwan ◽

Shahriar Jalal Nibir ◽

Md. Rifat Alam Siddique

Keyword(s):

Low Power ◽

Reduction Method ◽

Vlsi Design ◽

Portable Devices ◽

Ultra Low Power ◽

Leakage Reduction ◽

Low Power Vlsi Design

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A pulse-triggered TSPC flip-flop for high-speed low-power VLSI design applications

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187) ◽

10.1109/iscas.1998.706849 ◽

2002 ◽

Cited By ~ 2

Author(s):

Jinn-Shyan Wang ◽

Po-Hui Yang

Keyword(s):

Low Power ◽

High Speed ◽

Vlsi Design ◽

Flip Flop ◽

Low Power Vlsi Design

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A low-power VLSI design methodology for high bit-rate data communications over UTP channel

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187) ◽

10.1109/iscas.1998.705314 ◽

2002 ◽

Cited By ~ 1

Author(s):

M. Goez ◽

N.R. Shanbhag

Keyword(s):

Low Power ◽

Design Methodology ◽

Vlsi Design ◽

Data Communications ◽

Rate Data ◽

Bit Rate ◽

High Bit Rate ◽

Vlsi Design Methodology ◽

Low Power Vlsi Design

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