Hardware implementation issues of turbo decoders

This paper gives a general overview of the implementation aspects of turbo decoders. Although the parallel architecture of the turbo code is emphasized, the serial concatenated convolutional codes for the turbo decoder are discussed too. Considering the general structure of iterative decoders, the main features of the soft input and soft output algorithm, which are the heart of a turbo decoder, are observed. The efficient parallel architectures of turbo decoders are shown which allow high speed implementation. Apart from these, implementation aspects like quantization issues and stopping rules to increase the throughput as well as an evaluation of the various turbo decoders are discussed. Finally, we suggest a number of solutions to overcome the implementation issues as well as the complexities without affecting the high throughput rate. DOI: http://dx.doi.org/10.3329/bjsir.v47i3.13068 Bangladesh J. Sci. Ind. Res. 47(3), 327-332 2012

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Parallel architecture for high-speed Viterbi decoding of convolutional codes

Electronics Letters ◽

10.1049/el:19890595 ◽

1989 ◽

Vol 25 (14) ◽

pp. 887 ◽

Cited By ~ 2

Author(s):

Y.F. Zhang ◽

P. Csillag

Keyword(s):

High Speed ◽

Parallel Architecture ◽

Convolutional Codes ◽

Viterbi Decoding

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PEM-PCA: A Parallel Expectation-Maximization PCA Face Recognition Architecture

The Scientific World JOURNAL ◽

10.1155/2014/468176 ◽

2014 ◽

Vol 2014 ◽

pp. 1-16 ◽

Cited By ~ 11

Author(s):

Kanokmon Rujirakul ◽

Chakchai So-In ◽

Banchar Arnonkijpanich

Keyword(s):

Feature Extraction ◽

Face Recognition ◽

Expectation Maximization ◽

High Speed ◽

Expectation Maximization Algorithm ◽

Parallel Architecture ◽

Principal Component ◽

Eigenvalue Decomposition ◽

Computational Time ◽

Recognition Systems

Principal component analysis or PCA has been traditionally used as one of the feature extraction techniques in face recognition systems yielding high accuracy when requiring a small number of features. However, the covariance matrix and eigenvalue decomposition stages cause high computational complexity, especially for a large database. Thus, this research presents an alternative approach utilizing an Expectation-Maximization algorithm to reduce the determinant matrix manipulation resulting in the reduction of the stages’ complexity. To improve the computational time, a novel parallel architecture was employed to utilize the benefits of parallelization of matrix computation during feature extraction and classification stages including parallel preprocessing, and their combinations, so-called a Parallel Expectation-Maximization PCA architecture. Comparing to a traditional PCA and its derivatives, the results indicate lower complexity with an insignificant difference in recognition precision leading to high speed face recognition systems, that is, the speed-up over nine and three times over PCA and Parallel PCA.

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The Ultra High Speed LMS Algorithm Implemented on Parallel Architecture Suitable for Multidimensional Adaptive Filtering

Adaptive Filtering ◽

10.5772/25070 ◽

2011 ◽

Author(s):

Marwan Jaber

Keyword(s):

Adaptive Filtering ◽

High Speed ◽

Parallel Architecture ◽

Lms Algorithm ◽

Ultra High Speed

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Técnicas para la implementación de turbo decodificadores con baja latencia

Journal of Scientific and Technical Applications ◽

10.35429/jsta.2019.15.5.29.41 ◽

2019 ◽

pp. 29-41

Author(s):

Lennin Conrado Yllescas-Calderon ◽

Ramón Parra-Michel ◽

Luis F Gonzalez-Pérez

Keyword(s):

Channel Coding ◽

Iterative Decoding ◽

Turbo Coding ◽

Processing Capacity ◽

Turbo Decoding ◽

Turbo Decoder ◽

Transmission Rates ◽

Communications Systems ◽

Lte Advanced ◽

Turbo Decoders

Turbo coding is a channel coding technique that increases the capacity of communications systems, especially wireless and mobile. Due to its high correction capability, this technique is used in modern wireless communication standards such as 3GPP and LTE/LTE-Advanced. One of the features of these systems is the increase in data processing capacity, where transmission rates of up to 1 Gbps are specified. However, the turbo coding technique inherently presents a limited performance as a consequence of the turbo decoding process at the reception stage. The turbo decoder presents a high operation latency mainly caused by the iterative decoding process, the interleaver and deinterleaver stage and the estimation process of the information bits. In this work, we show the techniques used to implement modern low-latency turbo decoders suitable for 3G and 4G standards.

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