Logic Synthesis Strategy Oriented to Low Power Optimization

The article presents a synthesis strategy focused on low power implementations of combinatorial circuits in an array-type FPGA structure. Logic functions are described by means of BDD. A new form of the SWitch activity BDD diagram (SWBDD) is proposed, which enables a function decomposition to minimize the switching activity of circuits. The essence of the proposed idea lies in the proper ordering of the variables and cutting the diagram, ensuring the minimization of switching in the combination circuit. This article contains the results of experiments confirming the effectiveness of the developed concept of decomposition. They were performed on popular benchmarks using academic and commercial synthesis systems.

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Decomposition of multi-output functions oriented to configurability of logic blocks

Bulletin of the Polish Academy of Sciences Technical Sciences ◽

10.1515/bpasts-2017-0036 ◽

2017 ◽

Vol 65 (3) ◽

pp. 317-331 ◽

Cited By ~ 17

Author(s):

M. Kubica ◽

D. Kania

Keyword(s):

Logic Synthesis ◽

Original Method ◽

Technology Mapping ◽

Output Function ◽

Function Decomposition ◽

Synthesis Strategy ◽

The Way ◽

Logic Blocks

AbstractThe main goal of the paper is to present a logic synthesis strategy dedicated to an LUT-based FPGA. New elements of the proposed synthesis strategy include: an original method of function decomposition, non-disjoint decomposition, and technology mapping dedicated to configurability of logic blocks. The aim of all of the proposed synthesis approaches is the sharing of appropriately configured logic blocks. Innovation of the methods is based on the way of searching decomposition, which relies on multiple cutting of an MTBDD diagram describing a multi-output function. The essence of the proposed algorithms rests on the method of unicoding dedicated to sharing resources, searching non-disjoint decomposition on the basis of the partition of root tables, and choosing the levels of diagram cutting that will guarantee the best mapping to complex logic blocks. The methods mentioned above were implemented in the MultiDec tool. The efficiency of the analyzed methods was experimentally confirmed by comparing the synthesis results with both academic and commercial tools.

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Post-Mapping Transformations for Low-Power Synthesis

VLSI Design ◽

10.1155/1998/96768 ◽

1998 ◽

Vol 7 (3) ◽

pp. 289-301

Author(s):

Rajendran Panda ◽

Farid N. Najm

Keyword(s):

Power Optimization ◽

Logic Synthesis ◽

Transition Density ◽

Optimization Methods ◽

Asynchronous Circuits ◽

Total Power ◽

Circuit Switching ◽

Delay Model ◽

Switching Activity ◽

Arrival Times

We propose a logic synthesis system that includes power optimization after technology mapping. Our approach is unique in that our post-mapping logic transformations take into account information on circuit delay, capacitance, arrival times, glitches, etc., to provide much better accuracy than previously proposed technology-independent power optimization methods. By changing connections in a mapped circuit, we achieve power improvements up to 13% in case of area- or delay-optimized circuits, with reductions also in area and delay. We show that by applying the proposed technique on circuits that are already restructured for lower switching activity using the technique presented in [11], total power savings up to 59% in case of area-optimized circuits and 38% in case of delay-optimized circuits are achievable. The post-mapping transformations are based on the transition density model of circuit switching activity and the concept of permissible logic functions. The techniques presented here are applicable equally well to both synchronous and asynchronous circuits. The power measurements are done under a general delay model.

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