Vectored-Bloom Filter for IP Address Lookup: Algorithm and Hardware Architectures

The Internet Protocol (IP) address lookup is one of the most challenging tasks for Internet routers, since it requires to perform packet forwarding at wire-speed for tens of millions of incomming packets per second. Efficient IP address lookup algorithms have been widely studied to satisfy this requirement. Among them, Bloom filter-based approach is attractive in providing high performance. This paper proposes a high-speed and flexible architecture based on a vectored-Bloom filter (VBF), which is a space-efficient data structure that can be stored in a fast on-chip memory. An off-chip hash table is infrequently accessed, only when the VBF fails to provide address lookup results. The proposed architecture has been evaluated through both a behavior simulation with C language and a timing simulation with Verilog. The hardware implementation result shows that the proposed architecture can achieve the throughput of 5 million packets per second in a field programmable gate array (FPGA) operated at 100 MHz.

Download Full-text

Vectored-Bloom Filter Implemented on FPGA for IP Address Lookup

2019 International Conference on Electronics, Information, and Communication (ICEIC) ◽

10.23919/elinfocom.2019.8706399 ◽

2019 ◽

Cited By ~ 2

Author(s):

Hayoung Byun ◽

Qingling Li ◽

Hyesook Lim

Keyword(s):

Bloom Filter ◽

Ip Address ◽

Ip Address Lookup

Download Full-text

ipBF: A Fast and Accurate IP Address Lookup Using 3D Bloom Filter

Advances in Intelligent Systems and Computing - Intelligent Systems Design and Applications ◽

10.1007/978-3-030-16660-1_18 ◽

2019 ◽

pp. 182-191 ◽

Cited By ~ 1

Author(s):

Ripon Patgiri ◽

Samir Kumar Borgohain ◽

Sabuzima Nayak

Keyword(s):

Bloom Filter ◽

Ip Address ◽

Ip Address Lookup

Download Full-text

High-speed IP address lookup using balanced multi-way trees

Computer Communications ◽

10.1016/j.comcom.2005.12.002 ◽

2006 ◽

Vol 29 (11) ◽

pp. 1927-1935 ◽

Cited By ~ 8

Author(s):

Hyesook Lim ◽

Wonjung Kim ◽

Bomi Lee ◽

Changhoon Yim

Keyword(s):

High Speed ◽

Ip Address ◽

Ip Address Lookup

Download Full-text

Implementation of Embedded Floating Point Arithmetic Units on FPGA

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.550.126 ◽

2014 ◽

Vol 550 ◽

pp. 126-136

Author(s):

N. Ramya Rani

Keyword(s):

High Speed ◽

High Performance ◽

Floating Point ◽

Double Precision ◽

Embedded Computing ◽

Floating Point Arithmetic ◽

Field Programmable ◽

Programmable Gate Arrays ◽

Arithmetic Units ◽

Point Arithmetic

:Floating point arithmetic plays a major role in scientific and embedded computing applications. But the performance of field programmable gate arrays (FPGAs) used for floating point applications is poor due to the complexity of floating point arithmetic. The implementation of floating point units on FPGAs consumes a large amount of resources and that leads to the development of embedded floating point units in FPGAs. Embedded applications like multimedia, communication and DSP algorithms use floating point arithmetic in processing graphics, Fourier transformation, coding, etc. In this paper, methodologies are presented for the implementation of embedded floating point units on FPGA. The work is focused with the aim of achieving high speed of computations and to reduce the power for evaluating expressions. An application that demands high performance floating point computation can achieve better speed and density by incorporating embedded floating point units. Additionally this paper describes a comparative study of the design of single precision and double precision pipelined floating point arithmetic units for evaluating expressions. The modules are designed using VHDL simulation in Xilinx software and implemented on VIRTEX and SPARTAN FPGAs.

Download Full-text

Design of a Small-Sized High-Speed Data Storage Module Based on FPGA

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.912-914.1556 ◽

2014 ◽

Vol 912-914 ◽

pp. 1556-1560

Author(s):

Sheng Kun Li ◽

Cheng Qun Chu ◽

Hai Liang Chen ◽

Fang Ma

Keyword(s):

Data Storage ◽

Flash Memory ◽

High Speed ◽

High Performance ◽

Data Access ◽

Nand Flash ◽

Nand Flash Memory ◽

Storage Unit ◽

Field Programmable ◽

High Speed Data

The large-capacity, high-speed and low power consumption become the new requirements for the data storage systems. In this paper, a high-performance storage module based on multiple NAND flash memory chips is presented to real-time massive data acquisition system. In order to achieve the miniaturization dimension and the high-speed data storage design requirements, the paper presents a small size and high-speed storage unit based on NAND flash, where the dimensions of the module can reach 33mm×33mm and the maximum rate is up to 60MB/s. Ensuring continuous and reliable operation requires a dedicated buffering for the data transmission. We analyze the elements and peculiarities of the flash memory chip and propose a multi-way architecture to speed up data access. The design of a multilevel high-speed buffer structure based on the field programmable gate array (FPGA) technology is introduced in the paper. The proposed system can be applicable to some portable digital equipment.

Download Full-text

Dynamic Task Distribution Model for On-Chip Reconfigurable High Speed Computing System

International Journal of Reconfigurable Computing ◽

10.1155/2015/783237 ◽

2015 ◽

Vol 2015 ◽

pp. 1-12

Author(s):

Mahendra Vucha ◽

Arvind Rajawat

Keyword(s):

High Speed ◽

High Performance ◽

Real Life ◽

Computing System ◽

Distribution Model ◽

Design Parameters ◽

Dynamic Task ◽

Task Distribution ◽

Field Programmable ◽

On Chip

Modern embedded systems are being modeled as Reconfigurable High Speed Computing System (RHSCS) where Reconfigurable Hardware, that is, Field Programmable Gate Array (FPGA), and softcore processors configured on FPGA act as computing elements. As system complexity increases, efficient task distribution methodologies are essential to obtain high performance. A dynamic task distribution methodology based on Minimum Laxity First (MLF) policy (DTD-MLF) distributes the tasks of an application dynamically onto RHSCS and utilizes available RHSCS resources effectively. The DTD-MLF methodology takes the advantage of runtime design parameters of an application represented as DAG and considers the attributes of tasks in DAG and computing resources to distribute the tasks of an application onto RHSCS. In this paper, we have described the DTD-MLF model and verified its effectiveness by distributing some of real life benchmark applications onto RHSCS configured on Virtex-5 FPGA device. Some benchmark applications are represented as DAG and are distributed to the resources of RHSCS based on DTD-MLF model. The performance of the MLF based dynamic task distribution methodology is compared with static task distribution methodology. The comparison shows that the dynamic task distribution model with MLF criteria outperforms the static task distribution techniques in terms of schedule length and effective utilization of available RHSCS resources.

Download Full-text