Design of a Small-Sized High-Speed Data Storage Module Based on FPGA

2014 ◽  
Vol 912-914 ◽  
pp. 1556-1560
Author(s):  
Sheng Kun Li ◽  
Cheng Qun Chu ◽  
Hai Liang Chen ◽  
Fang Ma
Keyword(s):  
Data Storage ◽  
Flash Memory ◽  
High Speed ◽  
High Performance ◽  
Data Access ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Storage Unit ◽  
Field Programmable ◽  
High Speed Data

The large-capacity, high-speed and low power consumption become the new requirements for the data storage systems. In this paper, a high-performance storage module based on multiple NAND flash memory chips is presented to real-time massive data acquisition system. In order to achieve the miniaturization dimension and the high-speed data storage design requirements, the paper presents a small size and high-speed storage unit based on NAND flash, where the dimensions of the module can reach 33mm×33mm and the maximum rate is up to 60MB/s. Ensuring continuous and reliable operation requires a dedicated buffering for the data transmission. We analyze the elements and peculiarities of the flash memory chip and propose a multi-way architecture to speed up data access. The design of a multilevel high-speed buffer structure based on the field programmable gate array (FPGA) technology is introduced in the paper. The proposed system can be applicable to some portable digital equipment.

A Novel Bit-Flipping LDPC Decoder for Solid-State Data Storage

2014 ◽  
Vol 513-517 ◽  
pp. 2094-2098 ◽  
Author(s):  
Wen Zhe Zhao ◽  
Kai Zhao ◽  
Qiu Bo Chen ◽  
Min Jie Lv ◽  
Zuo Xun Hou
Keyword(s):  
Solid State ◽  
Error Correction ◽  
Data Storage ◽  
Flash Memory ◽  
Message Passing ◽  
High Speed ◽  
Design Solution ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
State Data

This paper concerns the design of high-speed and low-cost LDPC code bit-flipping decoder. Due to its inferior error correction strength, bit-flipping decoding received very little attention compared with message-passing decoding. Nevertheless, emerging flash-based solid-state data storage systems inherently favor a hybrid bit-flipping/message-passing decoding strategy, due to the significant dynamics and variation of NAND flash memory raw storage reliability. Therefore, for the first time highly efficient silicon implementation of bit-flipping decoder becomes a practically relevant topic. To address the drawbacks caused by the global search operation in conventional bit-flipping decoding, this paper presents a novel bit-flipping decoder design. Decoding simulations and ASIC design show that the proposed design solution can achieve upto 80% higher decoding throughput and meanwhile consume upto 50% less silicon cost, while maintaining almost the same decoding error correction strength.

High Performance NAND Flash Memory System with a Data Buffer

2013 ◽  
Vol E96.A (12) ◽  
pp. 2645-2651 ◽  
Author(s):  
Jung-Hoon LEE ◽  
Bo-Sung JUNG
Keyword(s):  
Flash Memory ◽  
High Performance ◽  
Memory System ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Data Buffer

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

2012 ◽  
Vol 47 (4) ◽  
pp. 981-989 ◽  
Author(s):  
Chulbum Kim ◽  
Jinho Ryu ◽  
Taesung Lee ◽  
Hyunggon Kim ◽  
Jaewoo Lim ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Performance ◽  
Nand Flash ◽  
Nand Flash Memory

Analysis and Realization of TLC or even QLC Operation with a High Performance Multi-times Verify Scheme in 3D NAND Flash memory

2018 ◽  
Author(s):  
C.C. Lu ◽  
C. C. Cheng ◽  
H.P. Chiu ◽  
W.L. Lin ◽  
T.W. Chen ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Performance ◽  
Nand Flash ◽  
Nand Flash Memory

The Application of Flash Memory in Computerized Jacquard Controller

2012 ◽  
Vol 182-183 ◽  
pp. 706-710 ◽  
Author(s):  
Cheng Jun Zhang ◽  
Xiao Yan Zuo ◽  
Chi Zhang ◽  
Xiao Guang Wu
Keyword(s):  
Flash Memory ◽  
High Speed ◽  
Data Transfer ◽  
Data Access ◽  
Management Procedures ◽  
File Structure ◽  
High Speed Data

Through analyzing the pattern data of computerized jacquard knitting wrap machine, comparing the current storages structure and type, this paper introduces a method for Flash file structure of jacquard data. The method takes advantage of ARM chip to achieve the operations for access and modification of Flash, designing a management procedures of jacquard data access from the perspective of increasing the Flash life. The management procedures not only complete read and write operations, but also meet the requirement of jacquard high-speed data transfer.

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