scholarly journals Reconfigurable Computing for Reactive Robotics Using Open-Source FPGAs

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 8
Author(s):  
José M. Cañas ◽  
Jesús Fernández-Conde ◽  
Julio Vega ◽  
Juan Ordóñez

Reconfigurable computing provides a paradigm to create intelligent systems different from the classic software computing approach. Instead of using a processor with an instruction set, a full stack of middleware, and an application program running on top, the field-programmable gate arrays (FPGAs) integrate a cell set that can be configured in different ways. A few vendors have dominated this market with their proprietary tools, hardware devices, and boards, resulting in fragmented ecosystems with few standards and little interoperation. However, a new and complete toolchain for FPGAs with its associated open tools has recently emerged from the open-source community. Robotics is an expanding application field that may definitely benefit from this revolution, as fast speed and low power consumption are usual requirements. This paper hypothesizes that basic reactive robot behaviors may be easily designed following the reconfigurable computing approach and the state-of-the-art open FPGA toolchain. They provide new abstractions such as circuit blocks and wires for building intelligent robots. Visual programming and block libraries make such development painless and reliable. As experimental validation, two reactive behaviors have been created in a real robot involving common sensors, actuators, and in-between logic. They have been also implemented using classic software programming for comparison purposes. Results are discussed and show that the development of reactive robot behaviors using reconfigurable computing and open tools is feasible, also achieving a high degree of simplicity and reusability, and benefiting from FPGAs’ low power consumption and time-critical responsiveness.

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Rajasekar P. ◽  
Mangalam H.

Purpose The growing trends in the usage of hand held devices necessitate the need to design them with low power consumption and less area design. Besides, information security is gaining enormous importance in information transmission and data storage technology. In addition, today’s technology world is connected, communicated and controlled via the Internet of Things (IoT). In many applications, the most standard and widely used cryptography algorithm for providing security is Advanced Encryption Standard (AES). This paper aims to design an efficient model of AES cryptography for low power and less area. Design/methodology/approach First, the main issues related to less area and low power consumption in the AES encryption core are addressed. To implement optimized AES core, the authors proposed optimized multiplicative inverse, affine transforms and Xtime multipliers functions, which are the core function of AES’s core. In addition, to achieve the high throughput, it uses the multistage pipeline and resource reuse architectures for SBox and Mixcolumn of AES. Findings The results of optimized AES architecture have revealed that the multistage pipe line and resource sharing are optimal design model in Field Programmable Gate Array (FPGA) implementation. It could provide high security with low power and area for IoT and wireless sensors networks. Originality/value This proposed optimized modified architecture has been implemented in FPGA to calculate the power, area and delay parameters. This multistage pipeline and resource sharing have promised to minimize the area and power.


Author(s):  
A. A. Mukhanbet ◽  
◽  
E. S. Nurakhov ◽  
B. S. Daribayev ◽  
◽  
...  

In recent years, some field programmable valve arrays (FPGAs) based on CNN release phase accelerators have been introduced. FPGA is widely used in portable devices. They can be programmed to achieve higher concurrency and provide better performance. The power consumption of the FPGA is lower than that of GPUs with the same workload. These reasons make the FPGA suitable for implementing the CNN release phase. They can provide relative output performance for GPUs and achieve low power consumption, which is very important for portable devices. To effectively implement the CNN output phase on the FPGA, the design should have high parallelism, and the hardware resources used should be minimized to reduce the area and power consumption. In the process of working with the help of a neural network, an algorithm for recognizing handwritten numbers is implemented. A special architecture is being created to implement a neural network at the appatent level. The performance during operation and power consumption is comparable to the performance of the processor and the GPU.


2021 ◽  
Author(s):  
Aman Kumar Tiwari ◽  
Priyanka Chaudhari ◽  
Shardul Pattewar ◽  
Rohini Deshmukh

An on-line monitoring system using LoRa based wireless technology for manhole cover is proposed. The system includes sensor sensing nodes, LoRaWAN network and application. LoRaWAN based IoT has very low power consumption for long-distance transmission. We use the accelerometer sensor to monitor the position, displacement or damage of manhole covers used in sewage systems. If these covers are moved or damaged, then LoRa board alerts the authorities LoRa gateway. The gateway is connected to The Things Network (TTN), a cloud-based crowd-funded open source LoRaWAN platform. The data is uploaded to the cloud and stored, and it will alert to the maintenance department. On TTN, our application will be launched and integrated with different features such as SMS.


2020 ◽  
Vol 64 (1-4) ◽  
pp. 165-172
Author(s):  
Dongge Deng ◽  
Mingzhi Zhu ◽  
Qiang Shu ◽  
Baoxu Wang ◽  
Fei Yang

It is necessary to develop a high homogeneous, low power consumption, high frequency and small-size shim coil for high precision and low-cost atomic spin gyroscope (ASG). To provide the shim coil, a multi-objective optimization design method is proposed. All structural parameters including the wire diameter are optimized. In addition to the homogeneity, the size of optimized coil, especially the axial position and winding number, is restricted to develop the small-size shim coil with low power consumption. The 0-1 linear programming is adopted in the optimal model to conveniently describe winding distributions. The branch and bound algorithm is used to solve this model. Theoretical optimization results show that the homogeneity of the optimized shim coil is several orders of magnitudes better than the same-size solenoid. A simulation experiment is also conducted. Experimental results show that optimization results are verified, and power consumption of the optimized coil is about half of the solenoid when providing the same uniform magnetic field. This indicates that the proposed optimal method is feasible to develop shim coil for ASG.


2016 ◽  
Vol 136 (11) ◽  
pp. 1555-1566 ◽  
Author(s):  
Jun Fujiwara ◽  
Hiroshi Harada ◽  
Takuya Kawata ◽  
Kentaro Sakamoto ◽  
Sota Tsuchiya ◽  
...  

Nano Letters ◽  
2013 ◽  
Vol 13 (4) ◽  
pp. 1451-1456 ◽  
Author(s):  
T. Barois ◽  
A. Ayari ◽  
P. Vincent ◽  
S. Perisanu ◽  
P. Poncharal ◽  
...  

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