scholarly journals Instability in In0.7Ga0.3As Quantum-Well MOSFETs with Single-Layer Al2O3 and Bi-Layer Al2O3/HfO2 Gate Stacks Caused by Charge Trapping under Positive Bias Temperature (PBT) Stress

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2039
Author(s):  
Hyuk-Min Kwon ◽  
Dae-Hyun Kim ◽  
Tae-Woo Kim

The instability of transistor characteristics caused by charge trapping under positive bias temperature (PBT) stress in In0.7Ga0.3As metal oxide semiconductor field-effect transistors (MOSFETs) with single-layer Al2O3 and bi-layer Al2O3/HfO2 gate stacks was investigated. The equivalent field across the multi-gate stacks was compared with a single layer used to compare the instability of electrical characteristics. The observed threshold voltage degradation (ΔVT) was consistent with the phenomenon of fast transient trapping of injected electrons at pre-existing shallow defects in the high-κ dielectric of HfO2, in which this charging was recovered by applying a relaxation voltage. Excluding the fast-transient charging components, the power law exponent (n), with respect to the time-dependent threshold voltage degradation, ranged from 0.3 to 0.35 for both single-layer Al2O3 and bi-layer Al2O3/HfO2 gate stacks. This long-term (slow) VT shift, which was strongly correlated with transconductance (Gm) degradation, was attributed to significant charge trapping in the border trap or/and defect sites within the high-κ dielectric.

2007 ◽  
Vol 54 (7) ◽  
pp. 1781-1783 ◽  
Author(s):  
Rahul Shringarpure ◽  
Sameer Venugopal ◽  
Zi Li ◽  
Lawrence T. Clark ◽  
David R. Allee ◽  
...  

2008 ◽  
Vol 29 (1) ◽  
pp. 93-95 ◽  
Author(s):  
Rahul Shringarpure ◽  
Sameer Venugopal ◽  
Lawrence T. Clark ◽  
David R. Allee ◽  
Edward Bawolek

2014 ◽  
Vol 61 (7) ◽  
pp. 2287-2293 ◽  
Author(s):  
Luca Vandelli ◽  
Luca Larcher ◽  
Dmitry Veksler ◽  
Andrea Padovani ◽  
Gennadi Bersuker ◽  
...  

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 427 ◽  
Author(s):  
Alejandro Campos-Cruz ◽  
Guillermo Espinosa-Flores-Verdad ◽  
Alfonso Torres-Jacome ◽  
Esteban Tlelo-Cuautle

Currently, researchers face new challenges in order to compensate or even reduce the noxious phenomenon known as bias-temperature instability (BTI) that is present in modern metal-oxide-semiconductor (MOS) technologies, which negatively impacts the performance of semiconductor devices. BTI remains a mystery in the way that it evolves in time, as well as the responsible mechanisms for its appearance and the further degradation it produces on MOS devices. The BTI phenomenon is usually associated with an increase of MOS transistor’s threshold voltage; however, this work also addresses BTI as a change in MOSFET’s drain current, transconductance, and the channel’s resistivity. In this way, we detail a physics-based model to get a better insight into the prediction of threshold voltage degradation for aging ranges going from days to years, in 180-nm MOS technology. We highlight that a physics-based BTI model improves accuracy in comparison to lookup table models. Finally, simulation results for the inclusion of such a physics-based BTI model into BSIM3v3 are shown in order to get a better understanding of how BTI impacts the performance of MOS devices.


Sign in / Sign up

Export Citation Format

Share Document