scholarly journals On the Prediction of the Threshold Voltage Degradation in CMOS Technology Due to Bias-Temperature Instability

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 427 ◽  
Author(s):  
Alejandro Campos-Cruz ◽  
Guillermo Espinosa-Flores-Verdad ◽  
Alfonso Torres-Jacome ◽  
Esteban Tlelo-Cuautle
Keyword(s):  
Threshold Voltage ◽  
Drain Current ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Lookup Table ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
Mos Devices ◽  
Voltage Degradation ◽  
Threshold Voltage Degradation

Currently, researchers face new challenges in order to compensate or even reduce the noxious phenomenon known as bias-temperature instability (BTI) that is present in modern metal-oxide-semiconductor (MOS) technologies, which negatively impacts the performance of semiconductor devices. BTI remains a mystery in the way that it evolves in time, as well as the responsible mechanisms for its appearance and the further degradation it produces on MOS devices. The BTI phenomenon is usually associated with an increase of MOS transistor’s threshold voltage; however, this work also addresses BTI as a change in MOSFET’s drain current, transconductance, and the channel’s resistivity. In this way, we detail a physics-based model to get a better insight into the prediction of threshold voltage degradation for aging ranges going from days to years, in 180-nm MOS technology. We highlight that a physics-based BTI model improves accuracy in comparison to lookup table models. Finally, simulation results for the inclusion of such a physics-based BTI model into BSIM3v3 are shown in order to get a better understanding of how BTI impacts the performance of MOS devices.

HOT CARRIER EFFECTS ON JITTER PERFORMANCE IN CMOS VOLTAGE-CONTROLLED OSCILLATORS

2006 ◽  
Vol 06 (03) ◽  
pp. L329-L334 ◽  
Author(s):  
CHI ZHANG ◽  
ASHOK SRIVASTAVA
Keyword(s):  
Threshold Voltage ◽  
Cmos Technology ◽  
Interface Traps ◽  
Voltage Controlled Oscillators ◽  
Hot Carrier ◽  
Hot Carrier Stress ◽  
Hot Carrier Effects ◽  
Voltage Degradation ◽  
Operation Frequency ◽  
Threshold Voltage Degradation

The effects of hot carrier stress on CMOS voltage-controlled oscillators (VCO) are investigated. A model of the threshold voltage degradation in MOSFETs due to hot carrier stress has been used to model jitter in voltage-controlled oscillators. The relation between the stress time which induces the hot carrier effects due to generation of interface traps near the drain of the n-MOSFETs, and the degradation of the VCO performance is presented. The VCO performance degradation takes into consideration decrease in operation frequency and increase in jitter. The experimental circuits have been designed in 0.5 μm n-well CMOS technology for operation at 3 V. Experimental results show that after four hours hot-carrier stress the jitter is increased by 40 ps for single-ended current starved VCOs.

Simulating the Influence of Mobile Ionic Oxide Charge on SiC MOS Bias-Temperature Instability Measurements

2015 ◽  
Vol 821-823 ◽  
pp. 697-700 ◽  
Author(s):  
Daniel B. Habersat ◽  
Neil Goldsman ◽  
Aivars J. Lelis
Keyword(s):  
Threshold Voltage ◽  
Drift Diffusion Model ◽  
Drift Diffusion ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
Mos Devices ◽  
The Impact ◽  
Ion Species ◽  
Ionic Oxide ◽  
Mos Device

We report here on results obtained using a time-dependent drift-diffusion model to simulate ion transport in the gate oxide of a SiC MOS device during bias-temperature instability measurements to assess the impact on threshold voltage under typical testing conditions. Measured threshold voltage is found to depend strongly on the temperature and mobile ion species, which in combination with the measurement parameters determine how the ions react to the stress and measurement sequence. Simulations show that, based on their mobilities, both potassium-like and copper-like ions may be responsible for experimental observations of a negative trend in threshold instability above 100 °C for SiC MOS devices.

scholarly journals Threshold Voltage Degradation for n-Channel 4H-SiC Power MOSFETs

2020 ◽  
Vol 10 (1) ◽  
pp. 3
Author(s):  
Esteban Guevara ◽  
Victor Herrera-Pérez ◽  
Cristian Rocha ◽  
Katherine Guerrero
Keyword(s):  
Silicon Carbide ◽  
Threshold Voltage ◽  
Measurement Data ◽  
Oxide Semiconductor ◽  
Damage Effect ◽  
Temperature Instability ◽  
Characterization Methods ◽  
Power Mosfets ◽  
Bias Temperature Instability ◽  
The Impact

In this study, threshold voltage instability on commercial silicon carbide (SiC) power metal oxide semiconductor field electric transistor MOSFETs was evaluated using devices manufactured from two different manufacturers. The characterization process included PBTI (positive bias temperature instability) and pulsed IV measurements of devices to determine electrical parameters’ degradations. This work proposes an experimental procedure to characterize silicon carbide (SiC) power MOSFETs following two characterization methods: (1) Using the one spot drop down (OSDD) measurement technique to assess the threshold voltage explains temperature dependence when used on devices while they are subjected to high temperatures and different gate voltage stresses. (2) Measurement data processing to obtain hysteresis characteristics variation and the damage effect over threshold voltage. Finally, based on the results, it was concluded that trapping charge does not cause damage on commercial devices due to reduced value of recovery voltage, when a negative small voltage is applied over a long stress time. The motivation of this research was to estimate the impact and importance of the bias temperature instability for the application fields of SiC power n-MOSFETs. The importance of this study lies in the identification of the aforementioned behavior where SiC power n-MOSFETs work together with complementary MOS (CMOS) circuits.

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