Instability in In0.7Ga0.3As Quantum-Well MOSFETs with Single-Layer Al2O3 and Bi-Layer Al2O3/HfO2 Gate Stacks Caused by Charge Trapping under Positive Bias Temperature (PBT) Stress

The instability of transistor characteristics caused by charge trapping under positive bias temperature (PBT) stress in In0.7Ga0.3As metal oxide semiconductor field-effect transistors (MOSFETs) with single-layer Al2O3 and bi-layer Al2O3/HfO2 gate stacks was investigated. The equivalent field across the multi-gate stacks was compared with a single layer used to compare the instability of electrical characteristics. The observed threshold voltage degradation (ΔVT) was consistent with the phenomenon of fast transient trapping of injected electrons at pre-existing shallow defects in the high-κ dielectric of HfO2, in which this charging was recovered by applying a relaxation voltage. Excluding the fast-transient charging components, the power law exponent (n), with respect to the time-dependent threshold voltage degradation, ranged from 0.3 to 0.35 for both single-layer Al2O3 and bi-layer Al2O3/HfO2 gate stacks. This long-term (slow) VT shift, which was strongly correlated with transconductance (Gm) degradation, was attributed to significant charge trapping in the border trap or/and defect sites within the high-κ dielectric.

MFMIS Negative Capacitance FinFET Design for Improving Drive Current

The effect of remnant polarization (Pr), coercive electric-field (Ec), and parasitic capacitance of baseline device on the drive current (ION) of a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) negative capacitance FinFET (NC FinFET) was investigated. The internal gate voltage in the MFMIS structure was simulated considering gate leakage current. Using technology computer aided design (TCAD) tool, the device characteristic of 7 nm FinFET was quantitatively estimated, for the purpose of modeling the baseline device of MFMIS NC FinFET. The need for appropriate parasitic capacitance to avoid performance degradation in MFMIS NC FinFET was presented through the internal gate voltage estimation. With an appropriate parasitic capacitance, the effect of Pr and Ec was investigated. In the case of Ec engineering, it is inappropriate to improve the device performance for MFMIS NC FinFET without threshold voltage degradation. Rather than Ec engineering, an adequate Pr value for achieving high ION in MFMIS NC FinFET is suggested.

Modeling of NBTI degradation in p-channel VDMOSFETs

This paper gives insight in reliability of p-channel VDMOSFET power transistors subjected to NBT stressing. Effects that lead to degradation of characteristics of these electronic circuits are presented, out of which threshold voltage shift with NBT stressing is further analysed. Measurements have been done and experimental results of the threshold voltage degradation of power transistors IRF9520 caused by different types of negative bias temperature stressing are shown. Stressing types, both static and pulsed, and their impact on transistors, especially on threshold voltage shifts have been explained in more details. An elementary equivalent electrical circuit is designed and proposed with the goal to model impact of both types of stressing, and also to calculate and estimate reliability of the circuit under specified stress. All of the elements of the modeling circuit and their dependencies are explained. Example of modeling from the experimental data is given together with the comparison between measured and modeled results. Differences between obtained results are discussed.

On the Prediction of the Threshold Voltage Degradation in CMOS Technology Due to Bias-Temperature Instability

Currently, researchers face new challenges in order to compensate or even reduce the noxious phenomenon known as bias-temperature instability (BTI) that is present in modern metal-oxide-semiconductor (MOS) technologies, which negatively impacts the performance of semiconductor devices. BTI remains a mystery in the way that it evolves in time, as well as the responsible mechanisms for its appearance and the further degradation it produces on MOS devices. The BTI phenomenon is usually associated with an increase of MOS transistor’s threshold voltage; however, this work also addresses BTI as a change in MOSFET’s drain current, transconductance, and the channel’s resistivity. In this way, we detail a physics-based model to get a better insight into the prediction of threshold voltage degradation for aging ranges going from days to years, in 180-nm MOS technology. We highlight that a physics-based BTI model improves accuracy in comparison to lookup table models. Finally, simulation results for the inclusion of such a physics-based BTI model into BSIM3v3 are shown in order to get a better understanding of how BTI impacts the performance of MOS devices.