scholarly journals VLSI Architecture for 8-Point AI-based Arai DCT having Low Area-Time Complexity and Power at Improved Accuracy

2012 ◽  
Vol 2 (2) ◽  
pp. 127-142 ◽  
Author(s):  
Amila Edirisuriya ◽  
Arjuna Madanayake ◽  
Vassil S. Dimitrov ◽  
Renato J. Cintra ◽  
Jithra Adikari
2014 ◽  
Vol 23 (10) ◽  
pp. 1450143 ◽  
Author(s):  
VIJAY K. SHARMA ◽  
K. K. MAHAPATRA ◽  
UMESH C. PATI

This paper presents non-recursive computation equation for 8 × 8 two-dimensional (2D) discrete cosine transform (DCT) along with novel VLSI architecture for direct computation of DCT without transposition memory. All intermediate operations are performed in non-fraction format. Being non-recursive and all intermediate calculations free of fractions, the proposed architecture has excellent accuracy in terms of peak signal-to-noise ratio (PSNR). The architecture is implemented in 0.18-μm CMOS standard cell technology library and prototyped in Field programmable gate array (FPGA) technology for the silicon validation. Implementation result shows that it has low power consumption and low area as compared to the available architectures of 2D DCT. To further increase the accuracy of computations, hardware overhead is very less as only one register and a multiplier bit-widths need to be changed.


Author(s):  
H.D. CHENG ◽  
X. CHENG

Shape recognition is an important research area in pattern recognition. It also has wide practical applications in many fields. An attribute grammar approach to shape recognition combines both the advantages of syntactic and statistical methods and makes shape recognition more accurate and efficient. However, the time complexity of a sequential shape recognition algorithm using attribute grammar is O(n3) where n is the length of an input string. When the problem size is very large it needs much more computing time, therefore a high speed parallel shape recognition is necessary to meet the demands of some real-time applications. This paper presents a parallel shape recognition algorithm and also discusses the algorithm partition problem as well as its implementation on a fixed-size VLSI architecture. The proposed algorithm has time complexity O(n3/k2) if using k×k processing elements. When k=n, its time complexity is O(n). The experiment has been conducted to verify the performance of the proposed algorithm. The correctness of the algorithm partition and the behavior of the proposed VLSI architecture have also been proved through the experiment. The results indicate that the proposed algorithm and the VLSI architecture could be very useful to imaging processing, pattern recognition and related areas, especially for real-time applications.


Author(s):  
Ida Nurhaida ◽  
Vina Ayumi ◽  
Devi Fitrianah ◽  
Remmy A. M. Zen ◽  
Handrie Noprisson ◽  
...  

One of the most famous cultural heritages in Indonesia is batik. Batik is a specially made drawing cloth by writing Malam (wax) on the cloth, then processed in a certain way. The diversity of motifs both in Indonesia and the allied countries raises new research topics in the field of information technology, both for conservation, storage, publication and the creation of new batik motifs. In computer science research area, studies about Batik pattern have been done by researchers and some algorithms have been successfully applied in Batik pattern recognition. This study was focused on Batik motif recognition using texture fusion feature which is Gabor, Log-Gabor, and GLCM; and using PCA feature reduction to improve the classification accuracy and reduce the computational time. To improve the accuracy, we proposed a Deep Neural Network model to recognise batik pattern and used batch normalisation as a regularises to generalise the model and to reduce time complexity. From the experiments, the feature extraction, selection, and reduction gave better accuracy than the raw dataset. The feature selection and reduction also reduce time complexity. The DNN+BN significantly improve the accuracy of the classification model from 65.36% to 83.15%. BN as a regularization has successfully made the model more general, hence improve the accuracy of the model. The parameters tuning also improved accuracy from 83.15% to 85.57%.


2015 ◽  
Author(s):  
Mohamed Ahmed ◽  
Michael Jeffers ◽  
John Feeney ◽  
Pardeep Govender ◽  
Mark Sherlock ◽  
...  

2006 ◽  
Vol 2 (1) ◽  
pp. 73-94 ◽  
Author(s):  
Péter Mészáros ◽  
David B. Funk

The Unified Grain Moisture Algorithm is capable of improved accuracy and allows the combination of many grain types into a single “unified calibration”. The purposes of this research were to establish processes for determining unifying parameters from the chemical and physical properties of grains. The data used in this research were obtained as part of the United States Department of Agriculture-Grain Inspection, Packers and Stockyards Administration's Annual Moisture Calibration Study. More than 5,000 grain samples were tested with a Hewlett-Packard 4291A Material/Impedance Analyzer. Temperature tests were done with a Very High Frequency prototype system at Corvinus University of Budapest. Typical chemical and physical parameters for each of the major grain types were obtained from the literature. Data were analyzed by multivariate chemometric methods. One of the most important unifying parameters (Slope) and the temperature correction coefficient were successfully modeled. The Offset and Translation unifying parameters were not modeled successfully, but these parameters can be estimated relatively easily through limited grain tests.


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