AN FPGA IMPLEMENTATION OF THE GPRS ENCRYPTION ALGORITHM 3 (GEA3)

2005 ◽  
Vol 14 (02) ◽  
pp. 217-231 ◽  
Author(s):  
P. KITSOS ◽  
M. D. GALANIS ◽  
O. KOUFOPAVLOU
Keyword(s):  
Hardware Implementation ◽  
Block Cipher ◽  
Data Encryption ◽  
Encryption Algorithm ◽  
General Packet Radio Service ◽  
Silicon Area ◽  
Double Edge ◽  
Hardware Implementations ◽  
Field Programmable ◽  
Significant Performance

The General Packet Radio Service (GPRS) uses the GPRS Encryption Algorithm 3 (GEA3) for data encryption. In this paper, alternative hardware implementations of the GEA3 algorithm are described. GEA3 algorithm is based on the KASUMI block cipher. Various KASUMI block cipher hardware implementations have been examined in order to provide information about the required silicon area and throughput. In order to achieve a significant performance improvement, Double Edge Triggered pipeline technique is used. The S-BOXes, which are fundamental elements of the KASUMI cipher, have been implemented by using combinational logic and ROM memories. The proposed GEA3 algorithm hardware implementation achieves throughput up to 837Mbps, which is much faster comparing to the previous designs. The whole system is implemented and evaluated by using Field Programmable Gate Array (FPGA) devices.

scholarly journals DES encryption and decryption algorithm implementation based on FPGA

2020 ◽  
Vol 18 (2) ◽  
pp. 774
Author(s):  
Subhi R. M. Zeebaree
Keyword(s):  
Data Security ◽  
Hardware Implementation ◽  
Block Cipher ◽  
Encryption Algorithm ◽  
The Internet ◽  
Clock Frequency ◽  
Hardware Implementations ◽  
Encryption And Decryption ◽  
Encryption Decryption ◽  
Algorithm Implementation

Nowadays there is a lot of importance given to data security on the internet. The DES is one of the most preferred block cipher encryption/decryption procedures used at present. This paper presents a high throughput reconfigurable hardware implementation of DES Encryption algorithm. This achieved by using a new proposed implementation of the DES algorithm using pipelined concept.  The implementation of the proposed design is presented by using Spartan-3E (XC3S500E) family FPGAs and is one of the fastest hardware implementations with much greater security. At a clock frequency of 167.448MHz for encryption and 167.870MHz for decryption, it can encrypt or decrypt data blocks at a rate of 10688Mbps.

A Novel Design and FPGA Implementation of Filters Adapted Using LMS Variants

2018 ◽  
Vol 27 (08) ◽  
pp. 1850125
Author(s):  
Sakshi ◽  
Ravi Kumar
Keyword(s):  
Interference Cancellation ◽  
Adaptive Filters ◽  
Hardware Implementation ◽  
Lms Algorithm ◽  
Variable Step Size ◽  
Step Size ◽  
Silicon Area ◽  
Novel Structure ◽  
Wide Range ◽  
Field Programmable

Adaptive filters have wide range of applications in areas such as echo or interference cancellation, prediction and system identification. Due to high computational complexity of adaptive filters, their hardware implementation is not an easy task. However, it becomes essential in many cases where real-time execution is needed. This paper presents the design and hardware implementation of a variable step size 40 order adaptive filter for de-noising acoustic signals. To ensure an area efficient implementation, a novel structure is being proposed. The proposed structure eliminates the requirement of extra registers for storage of delayed inputs thereby reducing the silicon area. The structure is compared with direct-form and transposed-form structures by adapting the filter coefficients using four different variants of the least means square (LMS) algorithm. Subsequently, the filters are implemented on three different field programmable gate arrays (FPGAs) viz. Spartan 6, Virtex 6 and Virtex 7 to find out the best device family that can be used to implement an Adaptive noise canceller (ANC) by comparing speed, power and area utilization. The synthesis results clearly reveal that ANC designed using the proposed structure has resulted in a reduction in silicon area without incurring any significant overhead in terms of power or delay.

scholarly journals FPGA Modeling and Optimization of a SIMON Lightweight Block Cipher

Sensors ◽  
2019 ◽  
Vol 19 (4) ◽  
pp. 913 ◽  
Author(s):  
Sa’ed Abed ◽  
Reem Jaffal ◽  
Bassam Mohd ◽  
Mohammad Alshayeji
Keyword(s):  
Block Cipher ◽  
Sensitive Data ◽  
Hardware Implementations ◽  
Balancing Energy ◽  
Field Programmable ◽  
Constrained Environments ◽  
Continuous Stream ◽  
Lightweight Block Cipher ◽  
The One ◽  
Least Area

Security of sensitive data exchanged between devices is essential. Low-resource devices (LRDs), designed for constrained environments, are increasingly becoming ubiquitous. Lightweight block ciphers provide confidentiality for LRDs by balancing the required security with minimal resource overhead. SIMON is a lightweight block cipher targeted for hardware implementations. The objective of this research is to implement, optimize, and model SIMON cipher design for LRDs, with an emphasis on energy and power, which are critical metrics for LRDs. Various implementations use field-programmable gate array (FPGA) technology. Two types of design implementations are examined: scalar and pipelined. Results show that scalar implementations require 39% less resources and 45% less power consumption. The pipelined implementations demonstrate 12 times the throughput and consume 31% less energy. Moreover, the most energy-efficient and optimum design is a two-round pipelined implementation, which consumes 31% of the best scalar’s implementation energy. The scalar design that consumes the least energy is a four-round implementation. The scalar design that uses the least area and power is the one-round implementation. Balancing energy and area, the two-round pipelined implementation is optimal for a continuous stream of data. One-round and two-round scalar implementations are recommended for intermittent data applications.

Hardware Implementation of AES Algorithm with Logic S-box

2017 ◽  
Vol 26 (09) ◽  
pp. 1750141 ◽  
Author(s):  
Soufiane Oukili ◽  
Seddik Bri
Keyword(s):  
Data Security ◽  
High Speed ◽  
Hardware Implementation ◽  
Network Applications ◽  
Aes Algorithm ◽  
Communication Techniques ◽  
High Speed Network ◽  
Cryptographic Algorithm ◽  
Hardware Implementations ◽  
Field Programmable

Cryptography has an important role in data security against known attacks and decreases or limits the risks of hacking information, especially with rapid growth in communication techniques. In the recent years, we have noticed an increasing requirement to implement cryptographic algorithms in fast rising high-speed network applications. In this paper, we present high throughput efficient hardware implementations of Advanced Encryption Standard (AES) cryptographic algorithm. We have adopted pipeline technique in order to increase the speed and the maximum operating frequency. Therefore, registers are inserted in optimal placements. Furthermore, we have proposed 5-stage pipeline S-box design using combinational logic to reach further speed. In addition, efficient key expansion architecture suitable for our proposed design is also presented. In order to secure the hardware implementation against side-channel attacks, masked S-box is introduced. The implementations had been successfully done by virtex-6 (xc6vlx240t) Field-Programmable Gate Array (FPGA) device using Xilinx ISE 14.7. Our proposed unmasked and masked architectures are very fast, they achieve a throughput of 93.73 Gbps and 58.57 Gbps, respectively. The obtained results are competitive in comparison with the implementations reported in the literature.

scholarly journals New primitives of controlled elements F2/4 for block ciphers

2020 ◽  
Vol 10 (5) ◽  
pp. 5470
Author(s):  
Minh Nguyen Hieu ◽  
Duy Ho Ngoc ◽  
Canh Hoang Ngoc ◽  
Trung Dinh Phuong ◽  
Manh Tran Cong
Keyword(s):  
Building Block ◽  
Hardware Implementation ◽  
Block Cipher ◽  
Block Ciphers ◽  
Differential Analysis ◽  
New Class ◽  
Use Of Data ◽  
Hardware Implementations ◽  
Bit Vector ◽  
Elementary Building

This paper develops the cipher design approach based on the use of data-dependent operations (DDOs). A new class of DDO based on the advanced controlled elements (CEs) is introduced, which is proven well suited to hardware implementations for FPGA devices. To increase the hardware implementation efficiency of block ciphers, while using contemporary FPGA devices there is proposed an approach to synthesis of fast block ciphers, which uses the substitution-permutation network constructed on the basis of the controlled elements F2/4 implementing the 2 x 2 substitutions under control of the four-bit vector. There are proposed criteria for selecting elements F2/4 and results on investigating their main cryptographic properties. It is designed a new fast 128-bit block cipher MM-128 that uses the elements F2/4 as elementary building block. The cipher possesses higher performance and requires less hardware resources for its implementation on the bases of FPGA devices than the known block ciphers. There are presented result on differential analysis of the cipher MM-128

AES Encryption Algorithm Hardware Implementation: Throughput and Area Comparison of 128, 192 and 256-bits Key

2012 ◽  
Vol 1 (2) ◽  
pp. 67 ◽  
Author(s):  
Samir El Adib ◽  
Naoufal Raissouni
Keyword(s):  
Hardware Implementation ◽  
Data Encryption ◽  
Encryption Algorithm ◽  
Advanced Encryption Standard ◽  
Data Encryption Standard ◽  
Security Applications ◽  
High Security ◽  
Aes Encryption Algorithm ◽  
Existing Data

<span lang="EN-US">Advanced Encryption Standard (AES) adopted by the National Institute of Standards and Technology (NIST) to replace existing Data Encryption Standard (DES), as the most widely used encryption algorithm in many security applications. Up to today, AES standard has key size variants of 128, 192, and 256-bit, where longer bit keys provide more secure ciphered text output. In the hardware perspective, bigger key size also means bigger area and small throughput. Some companies that employ ultra-high security in their systems may look for a key size bigger than 128-bit AES. In this paper, 128, 192 and 256-bit AES hardware are implemented and compared in terms of throughput and area. The target hardware used in this paper is Virtex XC5VLX50 FPGA from Xilinx. Total area and Throughput results are presented and graphically compared.</span>

Symmetric Encryption Algorithm Inspired by Randomness and Non-Linearity of Immune Systems

2012 ◽  
Vol 3 (1) ◽  
pp. 56-72 ◽  
Author(s):  
Suriyani Ariffin ◽  
Ramlan Mahmod ◽  
Azmi Jaafar ◽  
Muhammad Rezal Kamel Ariffin
Keyword(s):  
Block Cipher ◽  
Data Encryption ◽  
Encryption Algorithm ◽  
Advanced Encryption Standard ◽  
Symmetric Encryption ◽  
Immune Systems ◽  
Core Components ◽  
And Diffusion ◽  
Confusion And Diffusion ◽  
Diffusion Properties

In data encryption, the security of the algorithm is measured based on Shannon’s confusion and diffusion properties. This paper identifies the correspondences and highlights the essential computation elements on the basis of randomness and non-linearity of immune systems. These systems can be applied in symmetric encryption algorithm that satisfies the properties in designing a new symmetric encryption block cipher. The proposed symmetric encryption block cipher called the 3D-AES uses components of the Advanced Encryption Standard (AES) symmetric encryption block cipher and the new core components based on immune systems approaches. To ensure adequate high security of the systems in the world of information technology, the laboratory experiment results are presented and analyzed. They show that the randomness and non-linearity of the output in the 3D-AES symmetric encryption block cipher are comparable to the AES symmetric encryption block cipher.

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