A Proposed Cascaded Multilevel Inverter with R-Load at Different Carrier Frequencies

Cascaded multilevel inverter has the major problem as voltage imbalance across the capacitors connected in circuits which are acting like dc sources. The number of level generation depends on the number of DC sources and switches placed in cascaded multilevel inverter topology. In this proposed topology the positive levels and zero levels of the inverter have been explained. This topology also work in symmetrical condition. The topology is simulated in MATLAB and its THDs are calculated at different modulation index. The voltage stress and loss calculations are carried out at different carrier frequencies.

A new single‐phase cascaded multilevel inverter topology with reduced number of switches and voltage stress

International Transactions on Electrical Energy Systems ◽

10.1002/2050-7038.12191 ◽

2019 ◽

Vol 30 (2) ◽

Cited By ~ 6

Author(s):

Marif Daula Siddique ◽

Saad Mekhilef ◽

Noraisyah Mohamed Shah ◽

Adil Sarwar ◽

Mudasir Ahmed Memon

Keyword(s):

Single Phase ◽

Multilevel Inverter ◽

Voltage Stress ◽

A Direct-Connected Hybrid Cascaded Multilevel Inverter Topology

IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society ◽

10.1109/iecon43393.2020.9255285 ◽

2020 ◽

Author(s):

Abdullah M. Noman ◽

Abdulrahman I. Alolah ◽

Abdullrahman A. Al-Shamma'a ◽

Abdulaziz A. Alkuhayli

Keyword(s):

Multilevel Inverter ◽

2020 IEEE First International Conference on Smart Technologies for Power, Energy and Control (STPEC) ◽

Development of Cascaded Multilevel Inverter Topology

10.1109/stpec49749.2020.9297797 ◽

2020 ◽

Author(s):

Kalyani M. Gajbhiye ◽

Vijay B. Borghate ◽

Manisha Pandey ◽

Sidharth Sabyasachi ◽

Hari babu Gobburi

Keyword(s):

Multilevel Inverter ◽

Simulation and Analysis of Novel Extendable Multilevel Inverter Topology

Journal of Circuits System and Computers ◽

10.1142/s0218126619500890 ◽

2019 ◽

Vol 28 (06) ◽

pp. 1950089 ◽

Cited By ~ 2

Author(s):

V. Thiyagarajan ◽

P. Somasundaram ◽

K. Ramash Kumar

Keyword(s):

Single Phase ◽

Harmonic Distortion ◽

Multilevel Inverter ◽

Voltage Waveform ◽

Dc Voltage ◽

Switching Losses ◽

Comparison Results ◽

Symmetrical Condition ◽

Gate Driver ◽

Multilevel inverter (MLI) has become more popular in high power, high voltage industries owing to its high quality output voltage waveform. This paper proposes a novel single phase extendable type MLI topology. The term ‘extendable’ is included since the presented topology can be extended with maximum number of dc voltage sources to synthesize larger output levels. This topology can be operated in both symmetrical and asymmetrical conditions. The major advantages of the proposed inverter topology include minimum switching components, reduced gate driver circuits, less harmonic distortion and reduced switching losses. The comparative analysis based on the number of switches, dc voltage sources and conduction switches between the proposed topology and other existing topologies is presented in this paper. The comparison results show that the proposed inverter topology requires fewer components. The performance of the proposed MLI topology has been analyzed in both symmetrical and asymmetrical conditions. The simulation model is developed using MATLAB/SIMULINK software to verify the performance of the proposed inverter topology and also the feasibility of the presented topology during the symmetrical condition has been validated experimentally.

A study of symmetrical and various asymmetrical DC source configurations of a novel cascaded multilevel inverter topology

2018 Technologies for Smart-City Energy Security and Power (ICSESP) ◽

10.1109/icsesp.2018.8376715 ◽

2018 ◽

Cited By ~ 5

Author(s):

Saikat Kumar Maity ◽

Tapas Roy

Keyword(s):

Multilevel Inverter ◽

Developed cascaded multilevel inverter topology to minimise the number of circuit devices and voltage stresses of switches

IET Power Electronics ◽

10.1049/iet-pel.2013.0080 ◽

2014 ◽

Vol 7 (2) ◽

pp. 459-466 ◽

Cited By ~ 75

Author(s):

Ali Ajami ◽

Mohammad Reza Jannati Oskuee ◽

Ataollah Mokhberdoran ◽

Alex Van den Bossche

Keyword(s):

Multilevel Inverter ◽

New cascaded multilevel inverter topology with minimum number of switches

Energy Conversion and Management ◽

10.1016/j.enconman.2009.06.032 ◽

2009 ◽

Vol 50 (11) ◽

pp. 2761-2767 ◽

Cited By ~ 283

Author(s):

Ebrahim Babaei ◽

Seyed Hossein Hosseini

Keyword(s):

Multilevel Inverter ◽

Minimum Number ◽

Switched Capacitor Based Cascaded Half-Bridge Multilevel Inverter With Voltage Boosting Feature

CPSS Transactions on Power Electronics and Applications ◽

10.24295/cpsstpea.2021.00006 ◽

2021 ◽

Vol 6 (1) ◽

pp. 63-73

Author(s):

Hossein Khoun-Jahan ◽

Keyword(s):

Multilevel Inverter ◽

Inrush Current ◽

Switched Capacitor ◽

Multilevel Inverters ◽

Main Drawback ◽

Front End ◽

Simulation Results ◽

Resonant Capacitor ◽

Cascaded multilevel inverter (CMI) topology is prevalent in many applications. However, the CMI requires many switches and isolated dc sources, which is the main drawback of this type of inverter. As a result, the volume, cost and complexity of the CMI topology are increased and the efficiency is deteriorated. This paper thus proposes a switched-capacitor-based multilevel inverter topology with half-bridge cells and only one dc source. Compared to the conventional CMI, the proposed inverter uses almost half the number of switches, while maintaining a boosting capability. Additionally, the main drawback of switched-capacitor multilevel inverters is the capacitor inrush current. This problem is also averted in the proposed topology by using a charging inductor or quasi-resonant capacitor charging with a front-end boost converter. Simulation results and lab-scale experimental verifications are provided to validate the feasibility and viability of the proposed inverter topology.