scholarly journals Performance Analysis of Multi-Fault Tolerant on Multiprocessor System On-chip

2019 ◽  
Vol 8 (12S2) ◽  
pp. 226-230
Keyword(s):  
Performance Analysis ◽  
Fault Tolerant ◽  
System On Chip ◽  
Multiprocessor System ◽  
Networks On Chip ◽  
On Chip ◽  
Network Interfaces ◽  
Evaluation Techniques

As plan multifaceted nature increments and scale innovation into profound submicron region, the opportunity of harm and unhappiness in Networks-on-Chip (NoCs) prolonged element. On this artwork, we middle across the examination and evaluation techniques to improve the unwavering excellent and strength of Network Interfaces (NIs) in multiprocessor framework on-chip engineering primarily based totally Noc. NIS is going about as an interface the various center covered innovation and interchanges foundation; incorrect conduct of one in all them can impact, ultimately, the overall framework. On this paintings, proposes a version of utilitarian mistakes for NI components to assess their helplessness to mistakes. Showing levels tolerant affiliation that may be utilized to decrease the affects of each changeless and transitory blames in NI. Display trial reenactment with limited overhead can collect NI dependability equal to the best got via manner of utilizing a framework using 3 stylish secluded repetition techniques, even as putting aside to 48 percent in the place, just as growing noteworthy energy decrease.

scholarly journals Design and implementation of secured agent based NoC using shortest path routing algorithm

2019 ◽  
Vol 9 (2) ◽  
pp. 950
Author(s):  
Kendaganna Swamy S ◽  
Anand Jatti ◽  
Uma B. V.
Keyword(s):  
Shortest Path ◽  
High Performance ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
System On Chip ◽  
Multiprocessor System ◽  
Shortest Path Routing ◽  
Agent Based ◽  
On Chip ◽  
Fault Information

Network on chip (NoC) is a scalable interconnection architecture for every increasing communication demand between many processing cores in system on chip design. Reliability aspects are becoming an important issue in fault tolerant architecture. Hence there is a demand for fault tolerant Agent architecture with suitable routing algorithm which plays a vital role in order to enhance the NoC performance. The proposed fault tolerant Agent based NoC method is used to enhance the reliability and performance of the Multiprocessor System on Chip (MPSoC) design against faulty links and nodes. These agents are placed in hierarchical manner to collect, process, classify and distribute different fault information related to the faulty links and nodes of the network. This fault information is used for further packet routing in the network with the help of shortest path routing algorithm. In addition to this the agent will provide the security for the node by setting firewall, which then decides whether the packet has to be processed or not. This intern provides high performance, low latency NoC by avoiding deadlock and live lock with low area overhead.

Energy-Performance Analysis and Optimization for Networks-on-Chip

2014 ◽  
Vol 36 (5) ◽  
pp. 988-1003 ◽  
Author(s):  
Shuai ZHANG ◽  
Feng-Long SONG ◽  
Dong WANG ◽  
Zhi-Yong LIU ◽  
Dong-Rui FAN
Keyword(s):  
Performance Analysis ◽  
Energy Performance ◽  
Networks On Chip ◽  
On Chip

A high performance scalable fuzzy based modified Asymmetric Heterogene Multiprocessor System on Chip (AHt-MPSOC) reconfigurable architecture

2021 ◽  
pp. 1-12
Author(s):  
Arun Prasath Raveendran ◽  
Jafar A. Alzubi ◽  
Ramesh Sekaran ◽  
Manikandan Ramachandran
Keyword(s):  
High Performance ◽  
Standard Technique ◽  
System On Chip ◽  
Mixed Integer ◽  
Multiprocessor System ◽  
Compound System ◽  
Available Bandwidth ◽  
Mip Model ◽  
Fpga Chip ◽  
On Chip

This Ensuing generation of FPGA circuit tolerates the combination of lot of hard and soft cores as well as devoted accelerators on a chip. The Heterogene Multi-Processor System-on-Chip (Ht-MPSoC) architecture accomplishes the requirement of modern applications. A compound System on Chip (SoC) system designed for single FPGA chip, and that considered for the performance/power consumption ratio. In the existing method, a FPGA based Mixed Integer Programming (MIP) model used to define the Ht-MPSoC configuration by taking into consideration the sharing hardware accelerator between the cores. However, here, the sharing method differs from one processor to another based on FPGA architecture. Hence, high number of hardware resources on a single FPGA chip with low latency and power targeted. For this reason, a fuzzy based MIP and Graph theory based Traffic Estimator (GTE) are proposed system used to define New asymmetric multiprocessor heterogene framework on microprocessor (AHt-MPSoC) architecture. The bandwidths, energy consumption, wait and transmission range are better accomplished in this suggested technique than the standard technique and it is also implemented with a multi-task framework. The new Fuzzy control-based AHt-MPSoC analysis proves significant improvement of 14.7 percent in available bandwidth and 89.8 percent of energy minimized to various traffic scenarios as compared to conventional method.

scholarly journals Reliability analysis of a fault-tolerant RISC-V system-on-chip

2021 ◽  
Vol 125 ◽  
pp. 114346
Author(s):  
Douglas Almeida Santos ◽  
Lucas Matana Luza ◽  
Luigi Dilillo ◽  
Cesar Albenes Zeferino ◽  
Douglas Rossi Melo
Keyword(s):  
Reliability Analysis ◽  
Fault Tolerant ◽  
System On Chip ◽  
On Chip
Sign in / Sign up

Export Citation Format

Share Document