Performance Analysis of Mixed-Wall CNT Interconnects Using Colliding Bodies Optimization Technique

In recent years, carbon nanotube (CNT) interconnects have emerged as a potential alternative to copper interconnects due to their several magnificent properties. Due to fabrication issues, realization of densely packed CNTs with uniform diameters in a bundle structure is difficult to achieve. Consequently, it is advantageous to obtain a combination of CNTs with non-uniform diameters in the bundle, thereby leading to a densely packed mixed-wall CNT bundle (MWCB). In a MWCB structure, tube density plays a major role to determine the parasitic elements associated with the interconnects. For this, prospectively, colliding bodies optimization (CBO) technique has been incorporated. It is inferred from the study that the overall crosstalk noise, delay, and power dissipation of MWCB interconnect with higher tube density (i.e., obtained using CBO technique) are lesser than other CNT structures. Henceforth, it is determined from the proposed work that prospective CBO technique for advanced MWCB structure is highly efficient and effective for on-chip interconnects in IC designs.

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Crosstalk noise and performance analysis of WDM-based torus networks-on-chip

2017 IEEE International Conference on Manipulation, Manufacturing and Measurement on the Nanoscale (3M-NANO) ◽

10.1109/3m-nano.2017.8286273 ◽

2017 ◽

Cited By ~ 1

Author(s):

Shujian Wang ◽

Yiyuan Xie

Keyword(s):

Performance Analysis ◽

Crosstalk Noise ◽

Networks On Chip ◽

And Performance ◽

On Chip ◽

Torus Networks

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Performance analysis of single-walled carbon nanotube and multi-walled carbon nanotube in 32nm technology for on-chip interconnect applications

Fifth International Conference on Computing, Communications and Networking Technologies (ICCCNT) ◽

10.1109/icccnt.2014.6963141 ◽

2014 ◽

Author(s):

P. Murugeswari ◽

A. P. Kabilan ◽

M. Vaishnavi ◽

C. Divya

Keyword(s):

Carbon Nanotube ◽

Performance Analysis ◽

Single Walled Carbon Nanotube ◽

Single Walled Carbon ◽

Multi Walled Carbon Nanotube ◽

On Chip

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Effect of Current Mode Signaling in Carbon Nanotube On-Chip Interconnect

Journal of Nano Research ◽

10.4028/www.scientific.net/jnanor.45.42 ◽

2017 ◽

Vol 45 ◽

pp. 42-48 ◽

Cited By ~ 2

Author(s):

P. Murugeswari ◽

A.P. Kabilan ◽

V.E. Jayanthi

Keyword(s):

Carbon Nanotube ◽

Power Dissipation ◽

Equivalent Circuit Model ◽

Current Mode ◽

Optical Interconnect ◽

Voltage Mode ◽

Low Power Dissipation ◽

And Performance ◽

On Chip ◽

Power Delay Product

A novel signaling technique for on-chip carbon nanotube interconnect aiming a higher bitrate in the range of Terahertz (THz) with low power dissipation, employing the current mode signal transportation is proposed in this paper. The technique exploits the combined advantages of current mode signaling and carbon nanotube. Using the equivalent circuit model, the transfer function is derived for the current mode carbon nanotube interconnect. Current mode signaling through carbon nanotube interconnect is simulated in MATLAB and HSPICE to study its efficiency and performance. The results are compared with the existing voltage mode CNT, current mode copper and optical interconnect. The proposed current mode signaling for carbon nanotube interconnect achieves 102 times lesser power delay product and 90% lesser delay than voltage mode. It exhibits lesser delay, 1000 times in local and 1.2 times in global and lesser power delay product by the factor of 1000 as compared with optical interconnect.

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A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2008.2002682 ◽

2009 ◽

Vol 17 (9) ◽

pp. 1267-1274 ◽

Cited By ~ 9

Author(s):

Liang Zhang ◽

John M. Wilson ◽

Rizwan Bashirullah ◽

Lei Luo ◽

Jian Xu ◽

...

Keyword(s):

Power Dissipation ◽

Complementary Metal Oxide Semiconductor ◽

Current Mode ◽

Cmos Technology ◽

Oxide Semiconductor ◽

Signal Delay ◽

Crosstalk Noise ◽

High Data ◽

On Chip ◽

Bus Architecture

This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5-10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5-48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80-1.52 pJ/b. This work demonstrates a 15.0%-67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.

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