Performance comparison of cu/low-k, carbon nanotube, and optics for on-chip and off-chip interconnects

Geekbench is one of the most referenced cross-platform benchmarks in the mobile world. Most of its workloads are synthetic but some of them aim to simulate real-world behavior. In the mobile world, its microarchitectural behavior has been reported rarely since the hardware profiling features are limited to the public. As a popular mobile performance workload, it is hard to find Geekbench’s microarchitecture characteristics in mobile devices. In this paper, a thorough experimental study of Geekbench performance characterization is reported with detailed performance metrics. This study also identifies mobile system on chip (SoC) microarchitecture impacts, such as the cache subsystem, instruction-level parallelism, and branch performance. After the study, we could understand the bottleneck of workloads, especially in the cache sub-system. This means that the change of data set size directly impacts performance score significantly in some systems and will ruin the fairness of the CPU benchmark. In the experiment, Samsung’s Exynos9820-based platform was used as the tested device with Android Native Development Kit (NDK) built binaries. The Exynos9820 is a superscalar processor capable of dual issuing some instructions. To help performance analysis, we enable the capability to collect performance events with performance monitoring unit (PMU) registers. The PMU is a set of hardware performance counters which are built into microprocessors to store the counts of hardware-related activities. Throughout the experiment, functional and microarchitectural performance profiles were fully studied. This paper describes the details of the mobile performance studies above. In our experiment, the ARM DS5 tool was used for collecting runtime PMU profiles including OS-level performance data. After the comparative study is completed, users will understand more about the mobile architecture behavior, and this will help to evaluate which benchmark is preferable for fair performance comparison.

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Performance comparison of selected wired and wireless networks on chip architectures

2015 17th Conference of Open Innovations Association (FRUCT) ◽

10.1109/fruct.2015.7117974 ◽

2015 ◽

Author(s):

Maria Komar

Keyword(s):

Wireless Networks ◽

Performance Comparison ◽

Networks On Chip ◽

On Chip

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On-chip vacuum microtriode using carbon nanotube field emitters

Applied Physics Letters ◽

10.1063/1.1480884 ◽

2002 ◽

Vol 80 (20) ◽

pp. 3820-3822 ◽

Cited By ~ 95

Author(s):

C. Bower ◽

W. Zhu ◽

D. Shalom ◽

D. Lopez ◽

L. H. Chen ◽

...

Keyword(s):

Carbon Nanotube ◽

Field Emitters ◽

On Chip

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Integration of Al-Fill Processes for Contacts and VIAS

MRS Proceedings ◽

10.1557/proc-427-253 ◽

1996 ◽

Vol 427 ◽

Cited By ~ 9

Author(s):

H. J. Barth

Keyword(s):

High Pressure ◽

Chip Design ◽

Size And Shape ◽

Future Developments ◽

Pattern Density ◽

New Challenges ◽

On Chip ◽

Damascene Interconnects ◽

Low K ◽

Electrical Data

AbstractToday different Al-fill techniques are used for the fill of submicron contacts and vias. The integration aspects of the most promising approaches, Al-reflow, cold/hot Al-planarization and high pressure Al-fill (Forcefill) are compared to the widely used W-plug technique. The filling properties are discussed with respect to future applications in ULSI devices. Special attention is given to the barrier stability in contacts and the influence on patterning. Various electrical data and reliability results are compared to metallizations with W-plugs. The implications of the Al-fill processes on chip design, especially on the size and shape of holes, the pattern density, the possibility of producing stacked contacts/vias and the metal to contact/via overlap are considered also. In an outlook for future developments, e.g. the introduction of low k dielectrics, the inverse metallization architecture with (dual) damascene interconnects and the emerging Cu metallizations, Alfill processes are facing new challenges which will be discussed.

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On-Chip Electrical Breakdown of Metallic Nanotubes for Mass Fabrication of Carbon-Nanotube-Based Electronic Devices

IEEE Transactions on Nanotechnology ◽

10.1109/tnano.2008.2004624 ◽

2008 ◽

Vol 7 (5) ◽

pp. 624-627 ◽

Cited By ~ 7

Author(s):

Gyoung-Ho Buh ◽

Jea-Ho Hwang ◽

Eun-Kyoung Jeon ◽

Hye-Mi So ◽

Jeong-O Lee ◽

...

Keyword(s):

Carbon Nanotube ◽

Electrical Breakdown ◽

Electronic Devices ◽

On Chip

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Advanced 3D Packaging of Chips and Materials Integrity: Stress-Induced Effects and Mechanical Properties of New Ultra Low-k Dielectrics for On-Chip Interconnect Stacks

Key Engineering Materials ◽

10.4028/www.scientific.net/kem.592-593.563 ◽

2013 ◽

Vol 592-593 ◽

pp. 563-568

Author(s):

Christoph Sander ◽

Martin Gall ◽

Kong Boon Yeap ◽

Ehrenfried Zschech

Keyword(s):

Computing Time ◽

Orientation Dependence ◽

Chip Design ◽

Simulation Methodology ◽

3D Packaging ◽

Internal Mechanical Stress ◽

On Chip ◽

Physics Based Simulation ◽

Low K ◽

Chip Analysis

Managing the emerging internal mechanical stress in chips particularly if they are 3D-tscked is a key task to maintain performance and reliability of microelectronic products. Hence, a strong need of a physics-based simulation methodology/flow emerges. This physics-based simulation, however, requires materials parameters with high accuracy. A full-chip analysis can then be performed, balancing the need for local resolution and computing time. Therefore, effective composite-type materials data for several regions of interest are needed. Advanced techniques to measure FEA-and design-relevant properties such as local and effective Youngs modulus and effective CTE values were developed and described in this paper. These data show a clear orientation dependence, caused by the chip design.

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Modeling of Thermo-Mechanical Stresses in Copper Interconnect/Low-k Dielectric Systems

Advances in Electronic Packaging, Parts A, B, and C ◽

10.1115/ipack2005-73450 ◽

2005 ◽

Author(s):

Y.-L. Shen

Keyword(s):

Structural Integrity ◽

Temperature Response ◽

Future Generation ◽

Interface Fracture ◽

Deformation Pattern ◽

Barrier Layers ◽

Copper Interconnect ◽

On Chip ◽

Interconnect Systems ◽

Low K

Systematic finite element analyses are carried out to model the thermomechanical stresses in on-chip copper interconnect systems. Constitutive behavior of encapsulated copper films, determined by experimentally measuring the stress-temperature response during thermal cycling, is used in the model for predicting stresses in copper interconnect/low-k dielectric structures. Various combinations of oxide and polymer-based low-k dielectric schemes are considered. The evolution of stresses and deformation pattern in the dual-damascene copper, barrier layers, and the dielectrics is seen to have direct connections to the structural integrity of contemporary and future-generation devices. In particular, stresses experienced by the thin barrier layers and the mechanically weak low-k dielectrics are critically assessed. A parametric analysis on the influence of low-k material properties is also conducted. Practical implications in reliability issues such as voiding, interface fracture, electromigration and dielectric failure are discussed.

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