Bundled SWCNT for Global VLSI Interconnects

Carbon nanotube (CNT) has been declared the most attractive and suitable material for VLSI sub-micron technology. Because of CNT's phenomenal physical, electrical, and mechanical properties, it is more advantageous than copper interconnect material. In this chapter, RLC equivalent model of bundled single-wall CNT (SWCNT) is presented by using driver-interconnect-load (DIL) system with CMOS driver. The crosstalk delay is calculated for two-line bus architecture made of two parallel lines (i.e., upper as aggressor and lower as victim). From the simulation, it has been observed that crosstalk delay increases with increase in interconnect length and transition time, whereas it decreases with increased spacing between the lines (aggressor and victim). However, crosstalk delay decreases as the number of tubes in a bundle increases.

CNT as Interconnects

The chapter will start with brief introduction to the interconnects and its importance in an integrated circuit at deep sub-micron technology nodes. The brief discussion about the concept of scaling, interconnects models, and material in use are presented. The limitations of conventional materials at scaled down technology nodes will be discussed next. The focus of the chapter is to present the electrical equivalent circuit model to estimate the impedance parameters of SWCNT bundle and MWCNT bundle as interconnects at different nano-scaled technology nodes for global level interconnect length. Using ESC model of SWCNT, MWCNT, and copper, the performance comparative analysis for delay and power delay product (PDP) will be presented for different interconnect lengths at nano-scaled technology nodes. Finally, the chapter summary and conclusion will be written at the end of the chapter.

CNTFET-Based Memory Design

As the feature size of device has been scaling down for many decades, conventional CMOS technology-based static random access memory (SRAM) has reached its limit due to significant leakage power. Therefore, carbon nanotube field effect transistor (CNTFET) can be considered most suitable alternative for SRAM. In this chapter, the performance and stability of CNTFET-based SRAM cells have been analyzed. Numerous figures of merit (FOM) (e.g., read/write noise margin, power dissipation, and read/write delay) have been considered to analyze the performance of CNTFET-based. The static power consumption in CNTFET-based SRAM cell was compared with conventional complementary metal oxide semiconductor (CMOS)-based SRAM cell. Conventional CNTFET and tunnel CNTFET-based SRAMs have also been considered for comparison. From the simulation results, it is observed that tunnel CNTFET SRAM cells have shown improved FOM over conventional CNTFET 6T SRAM cells without losing stability.

Performance Analysis of Mixed-Wall CNT Interconnects Using Colliding Bodies Optimization Technique

In recent years, carbon nanotube (CNT) interconnects have emerged as a potential alternative to copper interconnects due to their several magnificent properties. Due to fabrication issues, realization of densely packed CNTs with uniform diameters in a bundle structure is difficult to achieve. Consequently, it is advantageous to obtain a combination of CNTs with non-uniform diameters in the bundle, thereby leading to a densely packed mixed-wall CNT bundle (MWCB). In a MWCB structure, tube density plays a major role to determine the parasitic elements associated with the interconnects. For this, prospectively, colliding bodies optimization (CBO) technique has been incorporated. It is inferred from the study that the overall crosstalk noise, delay, and power dissipation of MWCB interconnect with higher tube density (i.e., obtained using CBO technique) are lesser than other CNT structures. Henceforth, it is determined from the proposed work that prospective CBO technique for advanced MWCB structure is highly efficient and effective for on-chip interconnects in IC designs.

Low Power, High Performance CNTFET-Based SRAM Cell Designs

The main objective of this chapter is to provide high-performance, low-power solutions for VLSI system designers. As technology scales down to 32nm and below, the present CMOS technology has to face the scaling limit, such as the increased leakage power, SCEs, and so on. To overcome these limits, the researchers have experimented on other technologies, among which a CNT technology-based device called CNTFET has been evaluated as one of the promising replacements to CMOS technology. In any digital systems, memory is an integral part, and it is also the largest constituent. SRAM is a widely used memory. In today's ICs, SRAM is going to occupy 60-70% of the total chip area. In this connection, this chapter describes the design of CNTFET-based 6T SRAM cell using circuit-level leakage reduction techniques, named sleep transistor, forced stack, data-retention sleep transistor, and stacked sleep.

CNTFETs

In recent years, carbon nanotube (CNT) emerged as one of the promising materials that shows various advantages over silicon material (e.g., aggressive channel length scaling due to absence of mobility degradation, variable bandgap with single material, ultra-thin body device that is possible due to smaller diameter [1-3nm], and compatibility of CNT with high-k materials resulting in high ION). Moreover, CNTs show both metallic and semiconducting properties; hence, by using metallic CNTs, interconnects can be realized to fabricate a circuit purely consisting of CNTs. This chapter will provide introduction to carbon nanotubes field effect transistor (CNTFETs) starting from material properties of carbon nanotubes and followed by how it can be used as semiconductor channel in field effect transistor (MOSFET) to form CNTFET. The different types of CNTFETs will be discussed based on the type of CNT used along with their advantages and disadvantages.

Transport Properties of Silicene Nanotube- and Silicene Nanoribbon-Based FETs

Silicene is one of the most interesting nanomaterials. In this chapter, computational studies have been done on Silicene nanotube and nanoribbon-based FETs to analyze their transport properties. The FET is designed from armchair nanoribbon and single wall nanotube. The scattering region is capped by a dielectric and a metallic layer to form a gate. The conductance versus gate bias voltage, conductance versus temperature up to 2000K, and electrode temperature versus current characteristics are calculated and plotted along with the design of the equivalent model of the structure. Extended Huckel-based calculations were used, and the analysis shows the transport properties of both structures.

CNTFET-Based Ternary Logic Gates

In the recent digital designs, there are certain circumstances where energy efficiency and ease is required, and in such situations, ternary logic (or three-valued logic) is favored. Ternary logic is an auspicious supernumerary to the conventional binary (0, 1) logic design techniques as this one is possible to attain straightforwardness and energy efficiency. This chapter deals with the comparative analysis of CMOS and CNTFET-based ternary inverter and universal gates design. The simulation result is analyzed and validated with a Hailey simulation program with integrated circuit (HSPICE) simulations. The average delay and power consumption in CNTFET-based ternary inverter have been reduced by approximately 90.3% and 48.8% respectively, as compared to CMOS-based ternary inverter design. Likewise, delay is reduced by 50% and power gets 99% reduction in ternary CNTFET NAND gate as compared to CMOS-based ternary NAND gat. It is concluded that CNFETs are faster and consume less power compared to CMOS technology.

Carbon Nano Tube-Based Sensor Design for NEMS/MEMS Applications

This chapter deals with designing CNT-based piezoresistive pressure sensors with different boss sizes and with different configurations designed for low pressure range. The purpose for this work is to show a NEMS-based pressure sensor, which was analyzed by using ANSYS 17 software. The different combination of the diaphragm shows the improved performance of the pressure sensor in the case of CNT as compare to the silicon. This chapter is organized in sections, where section 2 discusses the review of CNT based MEMS/NEM design process and applications, Section 3 elaborates the use of CNT materials for design piezoresistive pressure sensors, Section 4 discusses mathematical modeling and simulation of CNT-based piezoresistive pressure sensors, Section 5 examines the results and discussion in terms of linearity and sensitivity of designed sensor, and Section 6 consummates the chapter with the conclusion.

CNTFET for Logic Gates Design

The novel characteristics of CNTFET have eliminated many technological and fundamental hindrances being faced by CMOS transistors. CNTFET is emerging as prospective replacement for CMOS transistors in digital circuits and systems. This chapter introduces design of CNTFET-based basic logic gates. The basic logic gates analyzed are inverter, NAND, and NOR gates. The designed gates are evaluated in terms of delay, power consumption, and figure-of-merit power-delay-product (PDP). The standard H-SPICE CNTFET model of Stanford University has been used for all simulations. The impact of dielectric material variations on performance parameters of carbon nanotube field effect transistor based universal gates has been analyzed. Comparison between CMOS and CNTFET-based logic circuits is carried out for different dielectric material at 16 nm technology node.