Numerical Model to Simulate the Drop Test of Printed Circuit Board (PCB)

Increasing demand for smaller consumer electronic devices with multi-function capabilities has driven the packaging architectures trends for the finer-pitch interconnects, thus increasing chances of their failures. A simulation of the Board Level Drop-Test according to JEDEC (Joint Electron Device Council) is performed to evaluate the solder joint reliability under drop impact test. After good insights to the physics of the problem, the results of the numerical analysis on a simple Euler-Bernoulli beam were validated against analytical analysis. Since the simulation has to be performed on ANSYS Mechanical which is an implicit software, two methods were proposed, the acceleration-input and the displacement-input. The results are the same for both methods. Therefore, the simulation is carried on the real standard model construction of the board package level2. Then a new improved model is proposed to satisfy shape regular element and accuracy. All the models are validated to show excellent first level correlation on the dynamic responses of Printed Circuit Board, and second level correlation on solder joint stress. Then a static model useful for quick design analysis and optimization’s works is proposed and validated. Finally, plasticity behavior is introduced on the solder ball and a non-linear analysis is performed.

Download Full-text

Experimental Investigation by Speckle Interferometry of Solder Joint Failure Under Thermomechanical Load Aggravated by Boundary Conditions at Board Level

Journal of Electronic Packaging ◽

10.1115/1.4007812 ◽

2012 ◽

Vol 134 (4) ◽

Cited By ~ 5

Author(s):

D. N. Borza ◽

I. T. Nistea

Keyword(s):

Solder Joint ◽

Fundamental Frequency ◽

Printed Circuit Board ◽

Speckle Interferometry ◽

Circuit Board ◽

Joint Failure ◽

Printed Circuit ◽

Out Of Plane ◽

Fringe Patterns ◽

Board Level

Reliability of electronic assemblies at board level and solder joint integrity depend upon the stress applied to the assembly. The stress is often of thermomechanical or of vibrational nature. In both cases, the behavior of the assembly is strongly influenced by the mechanical boundary conditions created by the printed circuit board (PCB) to casing fasteners. In many previously published papers, the conditions imposed to the fasteners are mostly aiming at an increase of the fundamental frequency and a decrease of static or dynamic displacement values characterizing the deformation. These conditions aim at reducing the fatigue in different parts of these assemblies. In the photomechanics laboratory of INSA Rouen, the origins of solder joint failure have been investigated by means of full-field measurements of the flexure deformation induced by vibrations or by forced thermal convection. The measurements were done both at a global level for the whole printed circuit board assembly (PCBA) and at a local level at the solder joints where failure was reported. The experimental technique used was phase-stepped laser speckle interferometry. This technique has a submicrometer sensitivity with respect to out-of-plane deformations induced by bending and its use is completely nonintrusive. Some of the results were comforted by comparison with a numerical finite elements model. The experimental results are presented either as time-average holographic fringe patterns, as in the case of vibrations, or as wrapped phase patterns, as in the case of deformation under thermomechanical stress. Both types of fringe patterns may be processed so as to obtain the explicit out-of-plane static deformation (or vibration amplitude) maps. Experimental results show that the direct cause of solder joint failure may be a high local PCB curvature produced by a supplementary fastening screw intended to reduce displacements and increase fundamental frequency. The curvature is directly responsible for tensile stress appearing in the leads of a large quad flat pack (QFP) component and for shear in the corresponding solder joints. The general principle of increasing the fundamental frequency and decreasing the static or dynamic displacement values has to be checked against the consequences on the PCB curvature near large electronic devices having high stiffness.

Download Full-text

Failure Analysis of Halogen-Free Printed Circuit Board Assembly Under Board-Level Drop Test

Journal of Electronic Packaging ◽

10.1115/1.4005956 ◽

2012 ◽

Vol 134 (1) ◽

Cited By ~ 2

Author(s):

Hung-Jen Chang ◽

Chau-Jie Zhan ◽

Tao-Chih Chang ◽

Jung-Hua Chou

Keyword(s):

Printed Circuit Board ◽

Drop Test ◽

Circuit Board ◽

Printed Circuit Board Assembly ◽

Printed Circuit ◽

Plastic Ball ◽

Circuit Board Assembly ◽

Halogen Free ◽

Board Level ◽

The Impact

In this study, a lead-free dummy plastic ball grid array component with daisy-chains and Sn4.0Ag0.5Cu Pb-free solder balls was assembled on an halogen-free high density interconnection printed circuit board (PCB) by using Sn1.0Ag0.5Cu solder paste on the Cu pad surfaces of either organic solderable preservative (OSP) or electroless nickel immersion gold (ENIG). The assembly was tested for the effect of the formation extent of Ag3Sn intermetallic compound. Afterward a board-level pulse-controlled drop test was conducted on the as-reflowed assemblies according to the JESD22-B110 and JESD22-B111 standards, the impact performance of various surface finished halogen-free printed circuit board assembly was evaluated. The test results showed that most of the fractures occurred around the pad on the test board first. Then cracks propagated across the outer build-up layer. Finally, the inner copper trace was fractured due to the propagated cracks, resulting in the failure of the PCB side. Interfacial stresses numerically obtained by the transient stress responses supported the test observation as the simulated initial crack position was the same as that observed.

Download Full-text

Experimental/numerical analysis of halogen-free printed circuit board assembly under board level drop test

2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference ◽

10.1109/impact.2009.5382197 ◽

2009 ◽

Cited By ~ 1

Author(s):

Chau-Jie Zhan ◽

Hung-Jen Chang ◽

Tao-Chih Chang ◽

Jung-Hua Chou

Keyword(s):

Numerical Analysis ◽

Printed Circuit Board ◽

Drop Test ◽

Circuit Board ◽

Printed Circuit Board Assembly ◽

Printed Circuit ◽

Circuit Board Assembly ◽

Halogen Free ◽

Board Level

Download Full-text

Materials Characterization of Lead Free Compositions for Minimum Temperature SMT Processes at the SLI-Second Level Interconnect Solder Joint

ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2004p0261 ◽

2004 ◽

Author(s):

Norman J. Armendariz ◽

Prawin Paulraj

Keyword(s):

Solder Joint ◽

Printed Circuit Board ◽

Gold Surface ◽

Circuit Board ◽

Lead Free ◽

Processing Temperature ◽

The European Union ◽

Printed Circuit ◽

Higher Temperature ◽

Tin Silver Copper

Abstract The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.

Download Full-text

Numerical Simulation and Experimental Measurement of a Printed Circuit Board Subjected to Drop Test

Key Engineering Materials ◽

10.4028/www.scientific.net/kem.419-420.37 ◽

2009 ◽

Vol 419-420 ◽

pp. 37-40

Author(s):

Shiuh Chuan Her ◽

Shien Chin Lan ◽

Chun Yen Liu ◽

Bo Ren Yao

Keyword(s):

Finite Element ◽

Experimental Measurement ◽

Test Specimen ◽

Printed Circuit Board ◽

Drop Impact ◽

Simulation Technique ◽

Drop Test ◽

Circuit Board ◽

Printed Circuit ◽

The Impact

Drop test is one of the common methods for determining the reliability of electronic products under actual transportation conditions. The aim of this study is to develop a reliable drop impact simulation technique. The test specimen of a printed circuit board is clamped at two edges on a test fixture and mounted on the drop test machine platform. The drop table is raised at the height of 50mm and dropped with free fall to impinge four half-spheres of Teflon. One accelerometer is mounted on the center of the specimen to measure the impact pulse. The commercial finite element software ANSYS/LS-DYNA is applied to compute the impact acceleration and dynamic strain on the test specimen during the drop impact. The finite element results are compared to the experimental measurement of acceleration with good correlation between simulation and drop testing. With the accurate simulation technique, one is capable of predicting the impact response and characterizing the failure mode prior to real reliability test.

Download Full-text