High-Speed Cyclic Bend Tests and Board-Level Drop Tests for Evaluating the Robustness of Solder Joints in Printed Circuit Board Assemblies

2009 ◽  
Vol 38 (6) ◽  
pp. 884-895 ◽  
Author(s):  
E.H. Wong ◽  
S.K.W. Seah ◽  
C.S. Selvanayagam ◽  
R. Rajoo ◽  
W.D. van Driel ◽  
...  
Keyword(s):  
High Speed ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Printed Circuit ◽  
Drop Tests ◽  
Bend Tests ◽  
Board Level

Understanding and Testing for Drop Impact Failure

2005 ◽  
Author(s):  
S. K. W. Seah ◽  
E. H. Wong ◽  
R. Ranjan ◽  
C. T. Lim ◽  
Y.-W. Mai
Keyword(s):  
Printed Circuit Board ◽  
Mechanical Response ◽  
Solder Joints ◽  
Drop Impact ◽  
Consumer Products ◽  
Circuit Board ◽  
Bga Packages ◽  
Response Board ◽  
Drop Tests ◽  
Board Level

This paper presents the results of experiments aimed at studying the effects of drop impact on portable electronics and reproducing these effects in controllable tests. Firstly, a series of drop tests were performed on consumer products (mobile phones and PDAs) to understand how the printed circuit board (PCB) within a product behaves in actual drop conditions. These product-level drop tests show that in drop impact, there are three possible types of mechanical response which can stress the 2nd level interconnections of CSP and BGA packages, namely: 1) flexing of the PCB on its supports, dominated by the 1st (fundamental) natural frequency; 2) flexing of the PCB resulting from direct impact or knocking against the PCB, typically dominated by higher natural frequencies; and 3) inertia loading on the solder joints due to high accelerations. Next, a series of board-level experiments were designed to separately study each of the three types of mechanical response. Board flexing due to direct impacts is the most severe response due to the strong strain amplitudes generated. Given the same input shock, the conventional board-level test — where the PCB flexes on its supports — produces much lower strain amplitudes. Inertia loading on the solder joints is practically negligible. Since PCB flexing is the main failure driver, a simple vibration test, which reproduces the strains observed in drop impact, is suggested as an alternative to time-consuming drop impact tests.

Experimental Investigation by Speckle Interferometry of Solder Joint Failure Under Thermomechanical Load Aggravated by Boundary Conditions at Board Level

2012 ◽  
Vol 134 (4) ◽  
Author(s):  
D. N. Borza ◽  
I. T. Nistea
Keyword(s):  
Solder Joint ◽  
Fundamental Frequency ◽  
Printed Circuit Board ◽  
Speckle Interferometry ◽  
Circuit Board ◽  
Joint Failure ◽  
Printed Circuit ◽  
Out Of Plane ◽  
Fringe Patterns ◽  
Board Level

Reliability of electronic assemblies at board level and solder joint integrity depend upon the stress applied to the assembly. The stress is often of thermomechanical or of vibrational nature. In both cases, the behavior of the assembly is strongly influenced by the mechanical boundary conditions created by the printed circuit board (PCB) to casing fasteners. In many previously published papers, the conditions imposed to the fasteners are mostly aiming at an increase of the fundamental frequency and a decrease of static or dynamic displacement values characterizing the deformation. These conditions aim at reducing the fatigue in different parts of these assemblies. In the photomechanics laboratory of INSA Rouen, the origins of solder joint failure have been investigated by means of full-field measurements of the flexure deformation induced by vibrations or by forced thermal convection. The measurements were done both at a global level for the whole printed circuit board assembly (PCBA) and at a local level at the solder joints where failure was reported. The experimental technique used was phase-stepped laser speckle interferometry. This technique has a submicrometer sensitivity with respect to out-of-plane deformations induced by bending and its use is completely nonintrusive. Some of the results were comforted by comparison with a numerical finite elements model. The experimental results are presented either as time-average holographic fringe patterns, as in the case of vibrations, or as wrapped phase patterns, as in the case of deformation under thermomechanical stress. Both types of fringe patterns may be processed so as to obtain the explicit out-of-plane static deformation (or vibration amplitude) maps. Experimental results show that the direct cause of solder joint failure may be a high local PCB curvature produced by a supplementary fastening screw intended to reduce displacements and increase fundamental frequency. The curvature is directly responsible for tensile stress appearing in the leads of a large quad flat pack (QFP) component and for shear in the corresponding solder joints. The general principle of increasing the fundamental frequency and decreasing the static or dynamic displacement values has to be checked against the consequences on the PCB curvature near large electronic devices having high stiffness.

Numerical Model to Simulate the Drop Test of Printed Circuit Board (PCB)

2011 ◽  
Vol 423 ◽  
pp. 26-30
Author(s):  
S. Assif ◽  
M. Agouzoul ◽  
A. El Hami ◽  
O. Bendaou ◽  
Y. Gbati
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Dynamic Responses ◽  
Circuit Board ◽  
Joint Stress ◽  
Printed Circuit ◽  
Increasing Demand ◽  
Improved Model ◽  
Board Level

Increasing demand for smaller consumer electronic devices with multi-function capabilities has driven the packaging architectures trends for the finer-pitch interconnects, thus increasing chances of their failures. A simulation of the Board Level Drop-Test according to JEDEC (Joint Electron Device Council) is performed to evaluate the solder joint reliability under drop impact test. After good insights to the physics of the problem, the results of the numerical analysis on a simple Euler-Bernoulli beam were validated against analytical analysis. Since the simulation has to be performed on ANSYS Mechanical which is an implicit software, two methods were proposed, the acceleration-input and the displacement-input. The results are the same for both methods. Therefore, the simulation is carried on the real standard model construction of the board package level2. Then a new improved model is proposed to satisfy shape regular element and accuracy. All the models are validated to show excellent first level correlation on the dynamic responses of Printed Circuit Board, and second level correlation on solder joint stress. Then a static model useful for quick design analysis and optimization’s works is proposed and validated. Finally, plasticity behavior is introduced on the solder ball and a non-linear analysis is performed.

Far End Crosstalk Mitigation of Differential High Speed Interconnects Within Printed Circuit Board Via Fields

2021 ◽  
Author(s):  
Junyan Tang ◽  
Xianbo Yang ◽  
Jose A. Hejase ◽  
Mahesh Bohra ◽  
Yanyan Zhang ◽  
...  
Keyword(s):  
High Speed ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Printed Circuit ◽  
High Speed Interconnects ◽  
Crosstalk Mitigation

Review of Printed-Circuit-Board Level EMI/EMC Issues and Tools

2010 ◽  
Vol 52 (2) ◽  
pp. 455-461 ◽  
Author(s):  
Bruce Archambeault ◽  
Colin Brench ◽  
Sam Connor
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Printed Circuit ◽  
Board Level

Reliability study of surface mount printed circuit board assemblies with lead‐free solder joints

2008 ◽  
Vol 20 (2) ◽  
pp. 30-38 ◽  
Author(s):  
Jeffery C.C. Lo ◽  
B.F. Jia ◽  
Z. Liu ◽  
J. Zhu ◽  
S.W. Ricky Lee
Keyword(s):  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Reliability Study ◽  
Surface Mount ◽  
Printed Circuit ◽  
Free Solder

Design of Equivalent Sampling Based on Printed Circuit Board Suited for Power Communication System

2013 ◽  
Vol 333-335 ◽  
pp. 465-471
Author(s):  
Chuan Liu ◽  
Zhi Chao Huang ◽  
Peng Wu ◽  
Lei Chen ◽  
Wei Wang
Keyword(s):  
Time Delay ◽  
Communication System ◽  
High Speed ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Transmission Time ◽  
Clock Signal ◽  
Signal Delay ◽  
Printed Circuit ◽  
Sequential Logic

Many applications in Power communication system have a demand of adjustable transmission time delay of high-speed signal. In sequential logic circuit, the control of transmission time delay of high-speed signal can effectively improve the accuracy of clock sampling, as a result, satisfy the constraints between clock signal and periodic data. A method of equivalent sampling based on printed circuit board (PCB) is provided in the article, it realizes equivalent sampling of the data by fixing a group of clock signal delay, thus, increase the accuracy of sampling.

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