On a Method of Getting Test Data for Boundary Scan Interconnection Test in Multiple Scan Chains

2014 ◽  
Vol 986-987 ◽  
pp. 1531-1535
Author(s):  
Xian Hua Yin ◽  
Cui Feng Xu
Keyword(s):  
Test Data ◽  
Test Time ◽  
Sorting Algorithm ◽  
Boundary Scan ◽  
Circuit Boards ◽  
Project Description ◽  
Description File ◽  
Multiple Scan ◽  
Scan Chains ◽  
Scan Chain

The goal of this paper is to present a new innovative method of getting test data for boundary scan interconnection test in multiple scan chains, so to decrease the test time and increase the efficiency and reliability. Firstly, a new model of configuring and optimizing multiple scan chains is formed based on the researches on greedy strategy for configuring multiple scan chains for internal test and the sorting algorithm of single scan chain for Cluster test. Then, a method of establishing test project description file (TPDF) is presented in order to get the test data quickly and effectively. During the testing of two different boundary-scan circuit boards, all faults can be detected. Experiment results show that the expected objective is achieved.

Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains

2008 ◽  
Vol 16 (7) ◽  
pp. 926-931 ◽  
Author(s):  
Xrysovalantis Kavousianos ◽  
Emmanouil Kalligeros ◽  
Dimitris Nikolos
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Test Data Compression ◽  
Multiple Scan ◽  
Scan Chains ◽  
Ip Cores

Test data decompression for multiple scan designs with boundary scan

1998 ◽  
Vol 47 (11) ◽  
pp. 1188-1200 ◽  
Author(s):  
J. Rajski ◽  
J. Tyszer ◽  
N. Zacharia
Keyword(s):  
Test Data ◽  
Boundary Scan ◽  
Multiple Scan

A New Wrapper Scan Chain Balance Algorithm for Intellectual Property in SoC

2014 ◽  
Vol 8 (1) ◽  
pp. 42-49
Author(s):  
Aijun Zhu ◽  
Zhi Li ◽  
Chuanpei Xu ◽  
Wangchun Zhu
Keyword(s):  
Intellectual Property ◽  
Optimization Algorithm ◽  
Test Time ◽  
Test Cost ◽  
Opposition Based Learning ◽  
Random Optimization ◽  
Mutation Operation ◽  
Scan Chains ◽  
Scan Chain ◽  
On Chip

Recent patents and progress on scan chain balance algorithms have been reviewed. With a significant increase of the SoC (System on Chip) integration and scale, the test time of SoC increase dramatically, and this makes the test cost of SoC grow rapidly. In order to reduce test cost and expense, the paper proposes an OBBO (Opposition-based learning and Biogeography Based Optimization) algorithm and designs wrapper scan chains for the IP(Intellectual Property) using OBBO algorithm, which can make wrapper scan chains equilibration so that we can make the test time of IP be minimum. The new method is a random optimization algorithm which combines BBO (Biogeography Based Optimization) algorithm with OBL (Opposition-based learning). By using migration operation, mutation operation and OBL operation, we achieve a balance between different wrapper chains so that we can shorten the wrapper scan chain which is longest. Experimental results show that OBBO can obtain shorter longest wrapper scan chain in most case and at the same time the convergence speed can be faster.

Representative Scan Architecture

2016 ◽  
Vol 25 (05) ◽  
pp. 1650040
Author(s):  
Ling Zhang ◽  
Jishun Kuang
Keyword(s):  
Integrated Circuits ◽  
Test Data ◽  
Switching Activity ◽  
Hardware Cost ◽  
Test Power ◽  
Test Set ◽  
Flip Flop ◽  
Chain Architecture ◽  
Multiple Scan ◽  
Scan Chain

Test power is one of the most challenges faced by Integrated Circuits. The author proposes a general scan chain architecture called Representative Scan (RS). It transforms the scan cells of conventional scan chain or sub-chain into circular shift registers and a representative flip-flop is chosen for each circular shift register, these representative flip-flops are connected serially to setup into the RS architecture. Thus, test data shifting path is shortened, then the switching activity is reduced in the shifting operates. The proposed scan architecture has the similar test power with the multiple scan chain, and only needs same test pins with single scan chain without added test pins. The experimental results show that the proposed scan architecture achieves very low shifting power. For benchmark circuits of ISCAS89, the shifting power of the best architecture of RS is only 0.53%–13.59% of the conventional scan. Especially for S35932, the shifting power on mintest test set is only 0.53% of the corresponding conventional scan. Compared with the conventional scan, the RS only needs to add a multiplexer for each scan cells, and the hardware cost is not high.

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