A New Wrapper Scan Chain Balance Algorithm for Intellectual Property in SoC

2014 ◽  
Vol 8 (1) ◽  
pp. 42-49
Author(s):  
Aijun Zhu ◽  
Zhi Li ◽  
Chuanpei Xu ◽  
Wangchun Zhu
Keyword(s):  
Intellectual Property ◽  
Optimization Algorithm ◽  
Test Time ◽  
Test Cost ◽  
Opposition Based Learning ◽  
Random Optimization ◽  
Mutation Operation ◽  
Scan Chains ◽  
Scan Chain ◽  
On Chip

Recent patents and progress on scan chain balance algorithms have been reviewed. With a significant increase of the SoC (System on Chip) integration and scale, the test time of SoC increase dramatically, and this makes the test cost of SoC grow rapidly. In order to reduce test cost and expense, the paper proposes an OBBO (Opposition-based learning and Biogeography Based Optimization) algorithm and designs wrapper scan chains for the IP(Intellectual Property) using OBBO algorithm, which can make wrapper scan chains equilibration so that we can make the test time of IP be minimum. The new method is a random optimization algorithm which combines BBO (Biogeography Based Optimization) algorithm with OBL (Opposition-based learning). By using migration operation, mutation operation and OBL operation, we achieve a balance between different wrapper chains so that we can shorten the wrapper scan chain which is longest. Experimental results show that OBBO can obtain shorter longest wrapper scan chain in most case and at the same time the convergence speed can be faster.

On a Method of Getting Test Data for Boundary Scan Interconnection Test in Multiple Scan Chains

2014 ◽  
Vol 986-987 ◽  
pp. 1531-1535
Author(s):  
Xian Hua Yin ◽  
Cui Feng Xu
Keyword(s):  
Test Data ◽  
Test Time ◽  
Sorting Algorithm ◽  
Boundary Scan ◽  
Circuit Boards ◽  
Project Description ◽  
Description File ◽  
Multiple Scan ◽  
Scan Chains ◽  
Scan Chain

The goal of this paper is to present a new innovative method of getting test data for boundary scan interconnection test in multiple scan chains, so to decrease the test time and increase the efficiency and reliability. Firstly, a new model of configuring and optimizing multiple scan chains is formed based on the researches on greedy strategy for configuring multiple scan chains for internal test and the sorting algorithm of single scan chain for Cluster test. Then, a method of establishing test project description file (TPDF) is presented in order to get the test data quickly and effectively. During the testing of two different boundary-scan circuit boards, all faults can be detected. Experiment results show that the expected objective is achieved.

scholarly journals Test Scheduling and Test Time Reduction for SoC by Using Enhanced Firefly Algorithm

2021 ◽  
Vol 35 (3) ◽  
pp. 265-271
Author(s):  
Gokul Chandrasekaran ◽  
Gopinath Singaram ◽  
Rajkumar Duraisamy ◽  
Akash Sanjay Ghodake ◽  
Parthiban Kunnathur Ganesan
Keyword(s):  
Firefly Algorithm ◽  
Base Material ◽  
Test Time ◽  
Test Scheduling ◽  
Testing Time ◽  
Test Cost ◽  
Test Cost Reduction ◽  
Test Time Reduction ◽  
Time Reduction ◽  
On Chip

System-on-Chip (SoC) is an integration of electronic components and billions of transistors. Defects due to the base material is caused during the manufacturing of components. To overcome these issues testing of chips is necessary but total cost increases because of increasing test time. The main issues to be considered during testing of SoC are the time taken for testing and accessibility of core. Effective test scheduling should be done to minimize testing time. In this paper, an effective test scheduling mechanism to minimize testing time is proposed. The test time reduction causes test cost reduction. The Enhanced Firefly algorithm is used in this paper to minimize test time. Enhanced Firefly algorithm gives a better result than Ant colony and Firefly algorithms in terms of test time reduction thereby reduction test cost takes place.

Failure Analysis Enhancement by Incorporating a Compact Scan Diagnosis System

2014 ◽  
Author(s):  
Rommel Estores ◽  
Pascal Vercruysse ◽  
Karl Villareal ◽  
Eric Barbian ◽  
Ralph Sanchez ◽  
...  
Keyword(s):  
Data Analysis ◽  
Failure Analysis ◽  
Real Analysis ◽  
Failure Data ◽  
Analysis Methodology ◽  
Efficiency And Effectiveness ◽  
Scan Chain ◽  
On Chip ◽  
Analysis Environment ◽  
Selection Of

Abstract The failure analysis community working on highly integrated mixed signal circuitry is entering an era where simultaneously System-On-Chip technologies, denser metallization schemes, on-chip dissipation techniques and intelligent packages are being introduced. These innovations bring a great deal of defect accessibility challenges to the failure analyst. To contend in this era while aiming for higher efficiency and effectiveness, the failure analysis environment must undergo a disruptive evolution. The success or failure of an analysis will be determined by the careful selection of tools, data and techniques in the applied analysis flow. A comprehensive approach is required where hardware, software, data analysis, traditional FA techniques and expertise are complementary combined [1]. This document demonstrates this through the incorporation of advanced scan diagnosis methods in the overall analysis flow for digital functionality failures and supporting the enhanced failure analysis methodology. For the testing and diagnosis of the presented cases, compact but powerful scan test FA Lab hardware with its diagnosis software was used [2]. It can therefore easily be combined with the traditional FA techniques to provide stimulus for dynamic fault localizations [3]. The system combines scan chain information, failure data and layout information into one viewing environment which provides real analysis power for the failure analyst. Comprehensive data analysis is performed to identify failing cells/nets, provide a better overview of the failure and the interactions to isolate the fault further to a smaller area, or to analyze subtle behavior patterns to find and rationalize possible faults that are otherwise not detected. Three sample cases will be discussed in this document to demonstrate specific strengths and advantages of this enhanced FA methodology.

Improving Yield Using Scan and DFT Based Analysis for High Performance PowerPC© Microprocessor

2006 ◽  
Author(s):  
Ray Talacka ◽  
Nandu Tendolkar ◽  
Cynthia Paquette
Keyword(s):  
High Performance ◽  
Yield Enhancement ◽  
Test Time ◽  
Balance Test ◽  
Specific Test ◽  
Defect Location ◽  
Test Methodology ◽  
Memory Arrays ◽  
Scan Chain ◽  
Scan Pattern

Abstract The use of memory arrays to drive yield enhancement has driven the development of many technologies. The uniformity of the arrays allows for easy testing and defect location. Unfortunately, the complexities of the logic circuitry are not represented well in the memory arrays. As technologies push to smaller geometries and the layout and timing of the logic circuitry become more problematic the ability to address yield issue is becoming critical. This paper presents the added yield enhancement capabilities of using e600 core Scan Chain and Scan Pattern testing for logic debug, ways to interpret the fail data, and test methodologies to balance test time and acquiring data. Selecting a specific test methodology and using today's advanced tools like Freescale's DFT/FA has been proven to find more yield issues, earlier, enabling quicker issue resolution.

Test scheduling of System-on-Chip using Dragonfly and Ant Lion optimization algorithms

2020 ◽  
pp. 1-13
Author(s):  
Gokul Chandrasekaran ◽  
P.R. Karthikeyan ◽  
Neelam Sanjeev Kumar ◽  
Vanchinathan Kumarasamy
Keyword(s):  
Ant Colony Optimization ◽  
Artificial Bee Colony ◽  
Optimization Algorithms ◽  
System On Chip ◽  
Test Time ◽  
Test Scheduling ◽  
Bee Colony ◽  
Ant Lion Optimization ◽  
Ant Lion ◽  
On Chip

Test scheduling of System-on-Chip (SoC) is a major problem solved by various optimization techniques to minimize the cost and testing time. In this paper, we propose the application of Dragonfly and Ant Lion Optimization algorithms to minimize the test cost and test time of SoC. The swarm behavior of dragonfly and hunting behavior of Ant Lion optimization methods are used to optimize the scheduling time in the benchmark circuits. The proposed algorithms are tested on p22810 and d695 ITC’02 SoC benchmark circuits. The results of the proposed algorithms are compared with other algorithms like Ant Colony Optimization, Modified Ant Colony Optimization, Artificial Bee Colony, Modified Artificial Bee Colony, Firefly, Modified Firefly, and BAT algorithms to highlight the benefits of test time minimization. It is observed that the test time obtained for Dragonfly and Ant Lion optimization algorithms is 0.013188 Sec for D695, 0.013515 Sec for P22810, and 0.013432 Sec for D695, 0.013711 Sec for P22810 respectively with TAM Width of 64, which is less as compared to the other well-known optimization algorithms.

scholarly journals Identifying the Optimal Subsets of Test Items through Adaptive Test for Cost Reduction of ICs

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 680
Author(s):  
Huaguo Liang ◽  
Jinlei Wan ◽  
Tai Song ◽  
Wangchao Hou
Keyword(s):  
Integrated Circuits ◽  
Cost Reduction ◽  
Bayesian Model ◽  
Test Methods ◽  
Test Time ◽  
Test Quality ◽  
Test Cost ◽  
Test Items ◽  
Adaptive Test ◽  
Test Escapes

With the growing complexity of integrated circuits (ICs), more and more test items are required in testing. However, the large number of invalid items (which narrowly pass the test) continues to increase the test time and, consequently, test costs. Aiming to address the problems of long test time and reduced test item efficiency, this paper presents a method which combines a fast correlation-based filter (FCBF) and a weighted naive Bayesian model which can identify the most effective items and make accurate quality predictions. Experimental results demonstrate that the proposed method reduces test time by around 2.59% and leads to fewer test escapes compared with the recently adopted test methods. The study shows that the proposed method can effectively reduce the test cost without jeopardizing test quality excessively.

Self-Adaptive Particle Swarm Optimization Algorithm with Mutation Operation Based on K-Means

2013 ◽  
Vol 760-762 ◽  
pp. 2194-2198 ◽  
Author(s):  
Xue Mei Wang ◽  
Yi Zhuo Guo ◽  
Gui Jun Liu
Keyword(s):  
Particle Swarm Optimization ◽  
Optimization Algorithm ◽  
Particle Swarm Optimization Algorithm ◽  
Particle Swarm ◽  
Local Optimum ◽  
Swarm Optimization ◽  
Adaptive Particle Swarm Optimization ◽  
Inertia Weight ◽  
Clustering Quality ◽  
Mutation Operation

Adaptive Particle Swarm Optimization algorithm with mutation operation based on K-means is proposed in this paper, this algorithm Combined the local searching optimization ability of K-means with the gobal searching optimization ability of Particle Swarm Optimization, the algorithm self-adaptively adjusted inertia weight according to fitness variance of population. Mutation operation was peocessed for the poor performative particle in population. The results showed that the algorithm had solved the poblems of slow convergence speed of traditional Particle Swarm Optimization algorithm and easy falling into the local optimum of K-Means, and more effectively improved clustering quality.

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