Simple Self-Aligned Fabrication Process for Silicon Carbide Static Induction Transistors

2004 ◽  
Vol 457-460 ◽  
pp. 1125-1128
Author(s):  
K. Dynefors ◽  
V. Desmaris ◽  
Joakim Eriksson ◽  
Per Åke Nilsson ◽  
Niklas Rorsman ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Fabrication Process ◽  
Static Induction Transistors ◽  
Static Induction

A novel self-aligned fabrication process for microwave static induction transistors in silicon carbide

2000 ◽  
Vol 21 (12) ◽  
pp. 578-580 ◽  
Author(s):  
J.P. Henning ◽  
A. Przadka ◽  
M.R. Melloch ◽  
J.A. Cooper
Keyword(s):  
Silicon Carbide ◽  
Fabrication Process ◽  
Static Induction Transistors ◽  
Static Induction

3 kV Normally-Off 4H-SiC Buried Gate Static Induction Transistors (SiC-BGSITs)

2014 ◽  
Vol 778-780 ◽  
pp. 899-902 ◽  
Author(s):  
Akio Takatsuka ◽  
Yasunori Tanaka ◽  
Koji Yano ◽  
Norio Matsumoto ◽  
Tsutomu Yatsuo ◽  
...  
Keyword(s):  
Leakage Current ◽  
Leakage Current Density ◽  
Current Density ◽  
Threshold Voltage ◽  
Room Temperature ◽  
Fabrication Process ◽  
Drain Voltage ◽  
Static Induction Transistors ◽  
Static Induction

3 kV normally-off SiC-buried gate static induction transistors (SiC-BGSITs) were fabricated by using an innovative fabrication process that was used by us previously to fabricate 0.7–1.2 kV SiC-BGSITs. The fabricated device shows the lowest specific on-resistance of 9.16 mΩ·cm2, compared to all other devices of the same class. The threshold voltage of this device was 1.4 V at room temperature and was maintained at values more than 1 V with normally-off characteristics at 200 °C. The device can block drain voltage of 3 kV with a leakage current density of 6.9 mA/cm2.

scholarly journals Improved Electrical Characteristics of Gallium Oxide/P-Epi Silicon Carbide Static Induction Transistors with UV/Ozone Treatment Fabricated by RF Sputter

Materials ◽  
2021 ◽  
Vol 14 (5) ◽  
pp. 1296
Author(s):  
Myeong-Cheol Shin ◽  
Young-Jae Lee ◽  
Dong-Hyeon Kim ◽  
Seung-Woo Jung ◽  
Michael A. Schweitz ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Photoelectron Spectroscopy ◽  
Gallium Oxide ◽  
Drain Current ◽  
Lower Surface ◽  
Ozone Treatment ◽  
Static Induction Transistors ◽  
Radio Frequency Sputtering ◽  
Static Induction ◽  
Uv Ozone

In this study, static induction transistors (SITs) with beta gallium oxide (β-Ga2O3) channels are grown on a p-epi silicon carbide (SiC) layer via radio frequency sputtering. The Ga2O3 films are subjected to UV/ozone treatment, which results in reduced oxygen vacancies in the X-ray photoelectron spectroscopy data, lower surface roughness (3.51 nm) and resistivity (319 Ω·cm), and higher mobility (4.01 cm2V−1s−1). The gate leakage current is as low as 1.0 × 10−11 A at VGS = 10 V by the depletion layer formed between n-Ga2O3 and p-epi SiC at the gate region with a PN heterojunction. The UV/O3-treated SITs exhibit higher (approximately 1.64 × 102 times) drain current (VDS = 12 V) and on/off ratio (4.32 × 105) than non-treated control devices.

RF and DC Characterization of Self-Aligned L-Band 4H-SiC Static Induction Transistors

2006 ◽  
Vol 527-529 ◽  
pp. 1223-1226 ◽  
Author(s):  
J. Neil Merrett ◽  
Igor Sankin ◽  
V. Bondarenko ◽  
C.E. Smith ◽  
D. Kajfez ◽  
...  
Keyword(s):  
Fabrication Process ◽  
Small Signal ◽  
Power Gain ◽  
Static Induction Transistors ◽  
Power Amplification ◽  
L Band ◽  
Static Induction ◽  
Power Densities ◽  
Load Pull

Trenched, vertical SiC static induction transistors (SIT) for L-band power amplification were fabricated with implanted p-n junction gates on conducting n-type 4H-SiC substrates using a self-aligned fabrication process. The self-aligned fabrication process required no critical alignments and allowed for high channel packing densities ranging from 2.9x103 to 5x103 cm/cm2. Devices were fabricated with a range of finger widths. Devices with the narrowest fingers were able to block up to 450 V with VGS = -3 V. Devices with wider fingers required higher gate voltages ranging from -10 V to -25 V to achieve similar blocking. Devices were packaged and small-signal and loadpull measurements were taken with the devices externally matched. Devices having the narrowest finger design had a small-signal power gain of over 9 dB at around 1.3 GHz. Load-pull measurements of packaged SITs with 1 cm gate periphery yielded a maximum power gain of ~ 8.2 dB at 1 GHz, VDD = 100 V, and VGS = 1.2 V. Due to the high packing density, these results translate to power densities of 22 kW/cm2.

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