Simulation Study of Single-Event Burnout for the 4H-SiC VDMOSFET with N+ Split Source

Silicon Carbide (SiC) power MOSFET is the next generation device in the supply system of spacecraft. However, the current degradation or catastrophic failure of the power device could be induced when a drain voltage exceeds critical condition. In this article, an improved VDMOSFET structure for the Single-Event Burnout (SEB) is demonstrated. The improved power VDMOSFET includes a P+ shielding region at the JFET region. Meanwhile, forming a CSL layer by ion-implantation at the JFET to reduce the specific on-resistance. The device is etched in both sides to form trench and then implanting N-type impurities at the side walls of the trench to form the N+ split source (SDS-VDMOSFET). The 2-D numerical simulator Silvaco Atlas was used to study the SEB performance for the 1.2 kV-rated SiC SDS-VDMOSFET in a high linear energy transfer (LET) value of 0.5 pC/μm. The simulation results show that the improved structure can effectively reduce the peak lattice temperature induced by heavy-ion and increase the SEB threshold voltage compared with the standard VDMOSFET. Furthermore, the improved structure also presents a lower specific on-resistance. As a result, the maximum temperature of the standard VDMOSFET has exceeded 3000 K at a drain voltage of 400 V. However, the maximum temperature of the improved VDMOSFET is only 2090 K at a drain voltage of 800 V.

Effect of Ge Concentration on the On-Current Boosting of Logic P-Type MOSFET with Sigma-Shaped Source/Drain

Silicon german ium (SiGe) has attracted significant attention for applications in the source/drain (S/D) regions of p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs). However, in SiGe, as the Ge concentration increases, high-density defects are generated, which limit its applications. Therefore, several techniques have been developed to minimize defects; however, these techniques require relatively thick epitaxial layers and are not suitable for gate-all-around FETs. This study examined the effect of Ge concentration on the embedded SiGe source/drain region of a logic p-MOSFET. The strain was calculated through nano-beam diffraction and predictions through a simulation were compared to understand the effects of stress relaxation on the change in strain applied to the Si channel. When the device performance was evaluated, the drain saturation current was approximately 710 µA/µm at an off current of 100 nA/µm with a drain voltage of 1 V, indicating that the current was enhanced by 58% when the Ge concentration was optimized.

Investigation into Class E/F3 with Parallel Network

The system of equations for processes in the amplifier output network is analytically formulated. This system of equations considers parameters of resonant networks at higher harmonics. To calculate amplifier output network, the system of five equations was built for five unknowns, to which the condition of positive second voltage derivative at extremum of drain voltage was added. Two equations correspond to class E conditions, another two — quadrature waveforms at load and at additional resonant network. The last equation is the condition of extremum at the point near middle of drain voltage pulse. This system was solved using computer algebra program. The circuit elements and waveforms were calculated using the derived parameters. By choosing different parameters, it is possible to obtain various amplifier realizations, which will demonstrate features of different class F variants. The obtained amplifier parameters drain voltage and current waveforms were verified with calculated ones using the harmonic balance simulating software. The variant, which is closer to class E/F3 mode, was chosen to build an experimental amplifier prototype on frequency 2MHz using IRF530 MOSFET as a switch. The prototype was tested in the range of supply dc voltage up to 24V with the output power greater than 6W, while the amplifier efficiency was >80%. In the experiment, the ratio of peak drain voltage to dc supply voltage was measured to be 3.3 at the duty ratio 50%, unlike class E amplifier, where this value is around 3.65, and on practice, considering non-linear drain to source capacitance, it may achieve 4. The experimental second harmonic level amounted to be -20 dB relatively to fundamental, and the third one — 28.5 dB, which is due to an additional second harmonic filter. The paper results are useful for introduction of such circuits to practice.

Evaluation of VTH and RON Drifts during Switch-Mode Operation in Packaged SiC MOSFETs

In this paper, we investigate the evolution of threshold voltage (VTH) and on-resistance (RON) drifts in the silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) during the switch-mode operation. A novel measurement setup for performing the required on-the-fly characterization is presented and the experimental results, obtained on commercially available TO-247 packaged SiC devices, are reported. Measurements were performed for 1000 s, during which negative VTH shifts (i.e., VTH decrease) and negative RON drifts (i.e., RON decrease) were observed. To better understand the origin of these parameter drifts and their possible correlation, measurements were performed for different (i) gate-driving voltage (VGH) and (ii) off-state drain voltage (VPH). We found that VTH reduction leads to a current increase, thus yielding RON to decrease. This correlation was explained by the RON dependence on the overdrive voltage (VGS–VTH). We also found that gate-related effects dominate the parameter drifts at low VPH with no observable recovery, due to the repeated switching of the gate signal required for the parameter monitoring. Conversely, the drain-induced instabilities caused by high VPH are completely recoverable within 1000 s from the VPH removal. These results show that the measurement setup is able to discern the gate/drain contributions, clarifying the origin of the observed VTH and RON drifts.