Reactive Ion Etching of Silicon Carbide with Patterned Boron Implantation

2004 ◽  
Vol 457-460 ◽  
pp. 925-928 ◽  
Author(s):  
Konstantin Vassilevski ◽  
J. Hedley ◽  
Alton B. Horsfall ◽  
C. Mark Johnson ◽  
Nicolas G. Wright
Materials ◽  
2021 ◽  
Vol 15 (1) ◽  
pp. 123
Author(s):  
Katarzyna Racka-Szmidt ◽  
Bartłomiej Stonio ◽  
Jarosław Żelazko ◽  
Maciej Filipiak ◽  
Mariusz Sochacki

The inductively coupled plasma reactive ion etching (ICP-RIE) is a selective dry etching method used in fabrication technology of various semiconductor devices. The etching is used to form non-planar microstructures—trenches or mesa structures, and tilted sidewalls with a controlled angle. The ICP-RIE method combining a high finishing accuracy and reproducibility is excellent for etching hard materials, such as SiC, GaN or diamond. The paper presents a review of silicon carbide etching—principles of the ICP-RIE method, the results of SiC etching and undesired phenomena of the ICP-RIE process are presented. The article includes SEM photos and experimental results obtained from different ICP-RIE processes. The influence of O2 addition to the SF6 plasma as well as the change of both RIE and ICP power on the etching rate of the Cr mask used in processes and on the selectivity of SiC/Cr etching are reported for the first time. SiC is an attractive semiconductor with many excellent properties, that can bring huge potential benefits thorough advances in submicron semiconductor processing technology. Recently, there has been an interest in SiC due to its potential wide application in power electronics, in particular in automotive, renewable energy and rail transport.


Vacuum ◽  
1995 ◽  
Vol 46 (4) ◽  
pp. 349-355 ◽  
Author(s):  
NJ Dartnell ◽  
MC Flowers ◽  
R Greef ◽  
J Zhu ◽  
A Blackburn

2012 ◽  
Vol 3 (1) ◽  
pp. 86 ◽  
Author(s):  
Yiyu Ou ◽  
Imran Aijaz ◽  
Valdas Jokubavicius ◽  
Rositza Yakimova ◽  
Mikael Syväjärvi ◽  
...  

Author(s):  
Jun Hai Xia ◽  
E. Rusli ◽  
R. Gopalakrishnan ◽  
S.F. Choy ◽  
Chin Che Tin ◽  
...  

2011 ◽  
Vol 679-680 ◽  
pp. 670-673 ◽  
Author(s):  
Konstantin Vassilevski ◽  
Irina P. Nikitina ◽  
Alton B. Horsfall ◽  
Nicolas G. Wright ◽  
Andrew J. Smith ◽  
...  

Trenched implanted vertical JFETs (TI-VJFETs) with self-aligned gate and source contacts were fabricated on commercial 4H-SiC epitaxial wafers. Gate regions were formed by aluminium implantation through the same silicon oxide mask which was used for etching mesa-structures. Self-aligned nickel silicide source and gate contacts were formed using a silicon oxide spacer formed on mesa-structure sidewalls by anisotropic thermal oxidation of silicon carbide followed by anisotropic reactive ion etching of oxide. Fabricated normally-on 4H-SiC TI-VJFETs demonstrated low gate leakage currents and blocking voltages exceeding 200 V.


Sign in / Sign up

Export Citation Format

Share Document