Novel Method for Evaluation of Negative Bias Temperature Instability of SiC MOSFETs

2019 ◽  
Vol 963 ◽  
pp. 749-752
Author(s):  
Jose Ortiz Gonzalez ◽  
Olayiwola Alatise ◽  
Philip A. Mawby
Keyword(s):  
Threshold Voltage ◽  
High Reliability ◽  
Gate Oxide ◽  
Gate Bias ◽  
Power Devices ◽  
Threshold Voltage Shift ◽  
Temperature Instability ◽  
Power Semiconductor ◽  
Bias Temperature Instability ◽  
Novel Method

The material properties of SiC make SiC power devices a superior alternative to the conventional Si power devices. However, the reliability of the gate oxide has been a major concern, limiting the adoption of SiC power MOSFETs as the power semiconductor of choice in applications which demand a high reliability. The threshold voltage (VTH) shift caused by Bias Temperature Instability (BTI) has focused the attention of different researchers, with multiple publications on this topic. This paper presents a novel method for evaluating the threshold voltage shift due to negative gate bias and its recovery when the gate bias stress is removed. This method could enable gate oxide reliability assessment techniques and contribute to new qualification methods.

Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET

2020 ◽  
Vol 1004 ◽  
pp. 554-558
Author(s):  
Kwangwon Lee ◽  
Young Ho Seo ◽  
Taeseop Lee ◽  
Kyeong Seok Park ◽  
Martin Domeij ◽  
...  
Keyword(s):  
High Temperature ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Gate Bias ◽  
Annealed Condition ◽  
Threshold Voltage Shift ◽  
Bias Stress ◽  
Phosphorus Doped ◽  
Gate Bias Stress ◽  
Gate Oxide Integrity

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

Effect of Fast Components in Threshold-Voltage Shift on Bias Temperature Instability in High-$k$ MOSFETs

2010 ◽  
Vol 31 (4) ◽  
pp. 287-289 ◽  
Author(s):  
Minseok Jo ◽  
Seonghyun Kim ◽  
Seungjae Jung ◽  
Ju-Bong Park ◽  
Joonmyoung Lee ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Threshold Voltage Shift ◽  
Temperature Instability ◽  
Voltage Shift ◽  
Bias Temperature Instability ◽  
High K
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