Low-Power, All Digital Phase-Locked Loop with a Wide-Range, High Resolution TDC

ETRI Journal ◽

10.4218/etrij.11.0110.0295 ◽

2011 ◽

Vol 33 (3) ◽

pp. 366-373 ◽

Author(s):

YoungGun Pu

Keyword(s):

High Resolution ◽

Low Power ◽

Phase Locked Loop ◽

Digital Phase ◽

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A low-power area-efficient wide-range offset calibration technique for high-speed high-resolution comparator

2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC) ◽

10.1109/edssc.2017.8333237 ◽

2017 ◽

Author(s):

Junxi Chen ◽

Shengqun Zheng ◽

Kai Sheng ◽

Weixin Gai ◽

Jianhua Feng

Keyword(s):

High Resolution ◽

Low Power ◽

Calibration Technique ◽

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Design of high-frequency wide-range all digital phase locked loop in 90 nm CMOS

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-013-0043-9 ◽

2013 ◽

Vol 75 (1) ◽

pp. 133-145 ◽

Author(s):

Prashanth Muppala ◽

Saiyu Ren ◽

George Yu-Heng Lee

Keyword(s):

High Frequency ◽

Phase Locked Loop ◽

Digital Phase ◽

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Design of a Low Power Schottky TTL High-Speed Digital Phase-Locked Loop Integrated Circuit.

10.21236/ada094729 ◽

1980 ◽

Author(s):

James D. Gallia

Keyword(s):

Low Power ◽

Integrated Circuit ◽

Phase Locked Loop ◽

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Energy Efficient All-Digital Phase Locked Loop Architecture Design on High Resolution Fast Clocking Time to Digital Converter (TDC) Using Model Prescient Control (MPC) Technique

Wireless Personal Communications ◽

10.1007/s11277-018-5371-8 ◽

2018 ◽

Vol 102 (4) ◽

pp. 3343-3359 ◽

Author(s):

T. M. Sathish Kumar ◽

P. S. Periasamy

Keyword(s):

High Resolution ◽

Energy Efficient ◽

Phase Locked Loop ◽

Architecture Design ◽

Digital Converter ◽

Time To Digital Converter ◽

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Design of a low power wide range phase locked loop using 180nm CMOS technology

2016 International Conference on Signal Processing and Communication (ICSC) ◽

10.1109/icspcom.2016.7980621 ◽

2016 ◽

Author(s):

Sreedhar Vineel R. Kaipu ◽

Kriti Vaish ◽

Sneha Komatireddy ◽

Akshat Sood ◽

Manish Goswami

Keyword(s):

Low Power ◽

Phase Locked Loop ◽

Cmos Technology ◽

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Design and Analysis of a Low Power Digital Phase Locked Loop

2016 8th International Conference on Computational Intelligence and Communication Networks (CICN) ◽

10.1109/cicn.2016.60 ◽

2016 ◽

Author(s):

Deepak Bhati ◽

Balwinder Singh

Keyword(s):

Low Power ◽

Phase Locked Loop ◽

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A 2.4-GHz low-power all-digital phase-locked loop

2009 IEEE Custom Integrated Circuits Conference ◽

10.1109/cicc.2009.5280832 ◽

2009 ◽

Author(s):

Liangge Xu ◽

Saska Lindfors ◽

Kari Stadius ◽

Jussi Ryynanen

Keyword(s):

Low Power ◽

Phase Locked Loop ◽

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Low-power digital phase locked loop utilizes CMOS logic

Microelectronics Reliability ◽

10.1016/0026-2714(72)90437-4 ◽

1972 ◽

Vol 11 (5) ◽

pp. 418

Keyword(s):

Low Power ◽

Phase Locked Loop ◽

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A 1.7mW All Digital Phase-Locked Loop with New Gain Generator and Low Power DCO

2006 IEEE International Conference on Acoustics Speed and Signal Processing Proceedings ◽

10.1109/iscas.2006.1693721 ◽

2006 ◽

Author(s):

Tzu-Chiang Chao ◽

Wei Hwang

Keyword(s):

Low Power ◽

Phase Locked Loop ◽

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A Low Power MICS Band Phase-Locked Loop for High Resolution Retinal Prosthesis

IEEE Transactions on Biomedical Circuits and Systems ◽

10.1109/tbcas.2012.2220545 ◽

2013 ◽

Vol 7 (4) ◽

pp. 513-525 ◽

Author(s):

Jiawei Yang ◽

Efstratios Skafidas

Keyword(s):

High Resolution ◽

Low Power ◽

Phase Locked Loop ◽

Retinal Prosthesis ◽

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