scholarly journals DECOUPLING LOGIC BASED SRAM DESIGN FOR POWER REDUCTION IN FUTURE MEMORIES

2014 ◽  
pp. 109-113
Author(s):  
M. PREMKUMAR ◽  
CH. JAYA PRAKASH
Keyword(s):  
Power Reduction ◽  
Sram Design ◽  
Nanometer Technology ◽  
Reduction Of Area

In this paper we are going to modify the column decoupled SRAM for the purpose of more reduced leakages than the existing type of designs as well as the new design which is combined of virtual grounding with column decoupling logic is compared with the existing technologies & the nanometer technology is also improved for the purpose of much improved reduction of area & power factors the simulations were done using microwind & DSCH results

scholarly journals A NEW LOW POWER TECHNOLOGY FOR POWER REDUCTION IN SRAM’S USING COLUMN DECOUPLING COMBINED WITH VIRTUAL GROUNDING

2013 ◽  
pp. 275-279
Author(s):  
SHAIK AHMADSAIDULU ◽  
PADALA SRINIVAS ◽  
SHAIK IDRISH
Keyword(s):  
Low Power ◽  
Power Reduction ◽  
Nanometer Technology ◽  
Reduction Of Area

In this paper we are going to modify the column decoupled SRAM for the purpose of more reduced leakages than the existing type of designs as well as the new design which is combined of virtual grounding with column decoupling logic is compared with the existing technologies & the nanometer technology is also improved for the purpose of much improved reduction of area & power factors the simulations were done using microwind& DSCH results.

scholarly journals A NEW LOW POWER TECHNOLOGY FOR POWER REDUCTION IN SRAM’S USING READ STABILITY WITH REDUCED TRANSISTOR COUNT FOR FUTURE CACHES

2014 ◽  
pp. 72-75
Author(s):  
K. HARI KRISHNA ◽  
P. HAREESH
Keyword(s):  
Low Power ◽  
Schmitt Trigger ◽  
Error Reduction ◽  
Power Reduction ◽  
Nanometer Technology ◽  
Reduction Of Area

In this paper we are going to modify the Schmitt Trigger based SRAM for the purpose of more reduced power & area than the existing type of designs as well as the new design which is combined of virtual grounding with read Error Reduction Logic is compared with the existing technologies & the nanometer technology is also improved for the purpose of much improved reduction of area & power factors than the Schmitt Trigger based SRAM Designs the simulations were done using microwind & DSCH results.

scholarly journals Trade-off for Leakage Power Reduction in Deep Sub Micron SRAM Design

2016 ◽  
Vol 4 (4) ◽  
pp. 110-117
Author(s):  
Tripti Tripathi ◽  
Dr. D. S. Chauhan ◽  
Dr. S. K. Singh
Keyword(s):  
High Speed ◽  
Digital Circuits ◽  
Power Reduction ◽  
Leakage Power ◽  
Cache Memory ◽  
Electronic Industry ◽  
Memory Design ◽  
Sram Cell ◽  
Sram Design ◽  
Processor Speed

Present day electronic industry faces the major problem of standby leakage current, as the processor speed increases, there is requirement of high speed cache memory. SRAM being mainly used for cache memory design, several low power techniques are being used for SRAM cell design. Full CMOS 6T SRAM cell is the most preferred choice for digital circuits. This paper reviews various leakage power techniques used in 6T SRAM cell and their comparative study.

LEAKAGE POWER REDUCTION USING MULTI MODAL DRIVEN HIERARCHICAL POWER MODE SWITCHES

2018 ◽  
Vol 6 (2) ◽  
pp. 1
Author(s):  
SEKHAR REDDY M. CHANDRA ◽  
REDDY P. RAMANA ◽  
◽  
Keyword(s):  
Power Reduction ◽  
Leakage Power ◽  
Power Mode

Stand-by Power Reduction Using Experimentally Demonstrated Nano-Electromechanical Switch in CMOS Technologies

2020 ◽  
pp. 1-7
Author(s):  
Sumit Saha ◽  
Arpit Singh ◽  
Maryam Shojaei Baghini ◽  
Mayank Goel ◽  
V. Ramgopal Rao
Keyword(s):  
Power Reduction

scholarly journals Low-Process–Voltage–Temperature-Sensitivity Multi-Stage Timing Monitor for System-on-Chip Applications

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1587
Author(s):  
Duo Sheng ◽  
Hsueh-Ru Lin ◽  
Li Tai
Keyword(s):  
High Performance ◽  
Power Reduction ◽  
System On Chip ◽  
Timing Information ◽  
Multi Stage ◽  
Dynamic Voltage ◽  
And Performance ◽  
On Chip ◽  
Maximum Measurement ◽  
Maximum Measurement Error

High performance and complex system-on-chip (SoC) design require a throughput and stable timing monitor to reduce the impacts of uncertain timing and implement the dynamic voltage and frequency scaling (DVFS) scheme for overall power reduction. This paper presents a multi-stage timing monitor, combining three timing-monitoring stages to achieve a high timing-monitoring resolution and a wide timing-monitoring range simultaneously. Additionally, because the proposed timing monitor has high immunity to the process–voltage–temperature (PVT) variation, it provides a more stable time-monitoring results. The time-monitoring resolution and range of the proposed timing monitor are 47 ps and 2.2 µs, respectively, and the maximum measurement error is 0.06%. Therefore, the proposed multi-stage timing monitor provides not only the timing information of the specified signals to maintain the functionality and performance of the SoC, but also makes the operation of the DVFS scheme more efficient and accurate in SoC design.

Buried Bitline for sub-5nm SRAM Design

2020 ◽  
Author(s):  
R. Mathur ◽  
M. Bhargava ◽  
S. Salahuddin ◽  
P. Schuddinck ◽  
J. Ryckaert ◽  
...  
Keyword(s):  
Sram Design
Sign in / Sign up

Export Citation Format

Share Document