scholarly journals Analysis and Simulation of Reduced FIR Filters

2005 ◽  
Vol 3 ◽  
pp. 365-369 ◽  
Author(s):  
Lj. Radic ◽  
W. Mathis

Abstract. High order FIR filters employ model reduction techniques, in order to decrease power consumption and time delay. During reduction high order FIR filters are converted into low order IIR filters preserving stability and phase linearity as main features. Matlab simulations of an audio system with these reduced filters are presented. Furthermore, the influence of order on power consumption is discussed.

Author(s):  
R. Michael Van Auken

The control of wheeled ground vehicle suspension systems is well suited for analysis and refinement using multi-input multi-output (MIMO) control law synthesis methods for linear systems. Usually it is necessary and desirable to develop the control algorithms using a reduced order model of the system. Since such vehicles are also characterized by correlated road inputs with time delay between the front and rear wheels, it is also desirable to consider this delay during the model reduction process. If this delay is taken into consideration, then it may be possible to develop low order control algorithms which compensate for the vehicle modes that are disturbed by the road inputs, resulting in improved overall performance. This paper describes the application of model reduction to a model of a ground vehicle for active suspension control law synthesis. The vehicle is described by a high order MIMO model of a “half-car” with four rigid-body degrees of freedom and flexible body modes to account for structural vibration, plus additional states to represent colored noise road disturbance inputs. Fourth order MIMO models suitable for control law synthesis are then determined using internal balancing, taking into consideration the time delay between the front and rear wheels, followed by subsystem elimination. The performance of the vehicle (high order model) with the resulting low order active suspension control laws is then assessed.


Author(s):  
Ziv Brand ◽  
Nadav Berman ◽  
Guy Rodnay

A method for designing small scale control laws for large scale thermal systems is proposed. For high order models, traditional control theory produces high order control laws, which are impractical to implement. Here, Balanced Truncation is used to reduce the order of the model, while preserving as much as possible the dynamical properties that are important for controller design. Then, a low order controller is designed by applying a standard linear quadratic optimal control design procedure on the reduced model. The small scale controller performance is tested by incorporating it in a simulation with the full scale model. A geometric approach is used, in order to propose that the norms that are defined on the input and output spaces of the system should be the same in the model reduction phase and in the optimal controller design phase. This way, the cost function of the optimal controller is taken into account during the model reduction phase. A reduced order observer which allows real time estimation of process values that cannot be directly measured can be easily designed. The input signals that are computed during closed loop simulation can be also used in real time open loop operation. Hence, the work has a pure computational aspect: calculate the heat fluxes that are required in order to track a temperature profile that is given for a set of output points. Integrating standard computational methods with standard control theory via the Balanced Truncation algorithm is proved to be a powerful tool.


Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.


2021 ◽  
Vol 40 (4) ◽  
pp. 1-15
Author(s):  
Siyuan Shen ◽  
Yin Yang ◽  
Tianjia Shao ◽  
He Wang ◽  
Chenfanfu Jiang ◽  
...  

2020 ◽  
Vol 53 (2) ◽  
pp. 4044-4051
Author(s):  
Jiacheng Song ◽  
Yongfeng Ju ◽  
Maode Yan ◽  
Panpan Yang ◽  
Lei Zuo

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