Effect of Gate-Recess Structure on Electron Transport in InP-Based High Electron Mobility Transistors Studied by Monte Carlo Simulations

2011 ◽  
Vol 50 (10R) ◽  
pp. 104302
Author(s):  
Akira Endoh ◽  
Issei Watanabe ◽  
Takashi Mimura ◽  
Toshiaki Matsui
VLSI Design ◽  
2001 ◽  
Vol 13 (1-4) ◽  
pp. 435-439 ◽  
Author(s):  
K. Kalna ◽  
A. Asenov ◽  
K. Elgaid ◽  
I. Thayne

The effect of scaling into deep decanano dimensions on the performance of pseudomorphic high electron mobility transistors (pHEMTs) is extensively studied using Monte Carlo simulations. The scaling of devices with gate lengths of 120, 70, 50 and 30nm is performed in both lateral and vertical directions. The devices exhibit a significant improvement in transconductance during scaling, even though external resistances become a limiting factor.


2015 ◽  
Vol 107 (15) ◽  
pp. 153504 ◽  
Author(s):  
Sanyam Bajaj ◽  
Omor F. Shoron ◽  
Pil Sung Park ◽  
Sriram Krishnamoorthy ◽  
Fatih Akyol ◽  
...  

2007 ◽  
Vol 46 (2) ◽  
pp. 478-484 ◽  
Author(s):  
Chih-Yuan Chan ◽  
Ting-Chi Lee ◽  
Shawn S. H. Hsu ◽  
Leaf Chen ◽  
Yu-Syuan Lin

2008 ◽  
Vol 155 (12) ◽  
pp. H987 ◽  
Author(s):  
Jung-Hun Oh ◽  
Min Han ◽  
Sung-Woon Moon ◽  
Seokhun Lee ◽  
In-Seok Hwang ◽  
...  

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