Investigation of the threshold voltage drift in enhancement mode GaN MOSFET under negative gate bias stress

2015 ◽  
Vol 54 (4) ◽  
pp. 044101 ◽  
Author(s):  
Fei Sang ◽  
Maojun Wang ◽  
Chuan Zhang ◽  
Ming Tao ◽  
Bing Xie ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Bias ◽  
Bias Stress ◽  
Enhancement Mode ◽  
Voltage Drift ◽  
Gate Bias Stress

1200 V SiC MOSFETs with Stable VTH under High Temperature Gate Bias Stress

2019 ◽  
Vol 963 ◽  
pp. 753-756
Author(s):  
Jimmy Franchi ◽  
Martin Domeij ◽  
Kwang Won Lee
Keyword(s):  
High Temperature ◽  
Threshold Voltage ◽  
High Field ◽  
Gate Oxide ◽  
Gate Bias ◽  
Bias Stress ◽  
Commercial Grade ◽  
Voltage Drift ◽  
Gate Bias Stress

In this work, threshold voltage drift of SiC MOSFET devices have been investigated. The drift during positive gate bias application was found to be moderate for three commercial grade devices, while the results for negative gate bias application differ widely. We demonstrate ON Semiconductor SiC MOSFETs with threshold voltage stability under both positive and negative bias stress due to an improved gate oxide process, and the influence of high field stress on the threshold voltage is additionally discussed. A long term transient high temperature gate bias stress is shown to cause a slight positive shift in the threshold voltage of the ON Semiconductor devices, while the on resistance remains constant.

Research on Threshold Voltage Instability in SiC MOSFET Devices with Precision Measurement

2019 ◽  
Vol 954 ◽  
pp. 133-138
Author(s):  
Ao Liu ◽  
Song Bai ◽  
Run Hua Huang ◽  
Tong Tong Yang ◽  
Hao Liu
Keyword(s):  
Threshold Voltage ◽  
Precision Measurement ◽  
Gate Dielectric ◽  
Interface Traps ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Experimental Platform ◽  
Bias Stress ◽  
Voltage Instability ◽  
Voltage Drift

The mechanism of threshold voltage shift was studied. It is believed that the instability in threshold voltage during gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. New experimental platform was designed and built successfully. When positive stress or negative stress is applied to the gate, the change of threshold voltage occur immediately. After stress removal, the recovery of the threshold voltage occur soon. The change and recovery of threshold voltage are very sensitive to time. In order to get accurate threshold voltage drift data after high-temperature gate bias experiment, test of threshold voltage must be carried out immediately after the experiment.

Dynamic Characterization of the Threshold Voltage Instability under the Pulsed Gate Bias Stress in 4H-SiC MOSFET

2017 ◽  
Vol 897 ◽  
pp. 549-552 ◽  
Author(s):  
Mitsuo Okamoto ◽  
Mitsuru Sometani ◽  
Shinsuke Harada ◽  
Hiroshi Yano ◽  
Hajime Okumura
Keyword(s):  
Threshold Voltage ◽  
High Speed ◽  
Stress Measurement ◽  
Measurement Instrument ◽  
Relaxation Effect ◽  
Gate Bias ◽  
Bias Stress ◽  
Speed Measurement ◽  
Gate Bias Stress

The threshold voltage (Vth) instability of 4H-SiC MOSFETs was investigated using high-speed IV measurement instrument. DC stress measurement of wide time span ranging from 10-6 to 103 s without relaxation effect was conducted. The high-speed measurement allowed of dynamic ΔVth measurement under pulsed AC gate bias stress. We investigated effects of NO POA in gate oxidation process on the Vth instabilities.

Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET

2020 ◽  
Vol 1004 ◽  
pp. 554-558
Author(s):  
Kwangwon Lee ◽  
Young Ho Seo ◽  
Taeseop Lee ◽  
Kyeong Seok Park ◽  
Martin Domeij ◽  
...  
Keyword(s):  
High Temperature ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Gate Bias ◽  
Annealed Condition ◽  
Threshold Voltage Shift ◽  
Bias Stress ◽  
Phosphorus Doped ◽  
Gate Bias Stress ◽  
Gate Oxide Integrity

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

The Influence of Temperature Storage on Threshold Voltage Stability for SiC VDMOSFET

2019 ◽  
Vol 954 ◽  
pp. 144-150
Author(s):  
Zhi Qiang Bai ◽  
Xiao Yan Tang ◽  
Chao Han ◽  
Yan Jing He ◽  
Qing Wen Song ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Voltage Stability ◽  
Stress Measurement ◽  
Gate Bias ◽  
Influence Of Temperature ◽  
Bias Stress ◽  
Negative Drift ◽  
The Difference ◽  
Temperature Storage ◽  
Gate Bias Stress

Even with SiC power MOSFETs released into the commercial market, the threshold voltage instability caused by near interface states is still an attracting issue, which is a major obstacle to further improving the device performance. In this paper, the effects of temperature storage on the threshold voltage stability of n-channel 4H-SiC VDMOSFET are studied. It is found that the capture of hole traps is dominant during the long-term temperature storage at 425 K, causing a considerable negative shift of threshold voltage. In view of the influence of temperature storage, the positive and negative drift trends of threshold voltage slow down during the gate-bias stress measurement. And the ∆VTH, the difference between the threshold voltages recorded after positive and negative gate-bias stress in the same duration, also grows slowly with the increasing stress duration. Finally, some suggestions for improving the threshold reliability of n-channel SiC VDMOSFETs are presented.

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