In recent years, 3D integration has become an alternative solution to the “More Moore” concept for providing circuits with higher performance or increased functionality.
Via-Middle TSV is considered a reference integration scheme and requires void-free copper fill of very high aspect ratio TSVs.
Metallization of such structures, in particular barrier and seed layer deposition, becomes a critical process step as barrier material to copper diffusion must provide good efficiency to copper diffusion for further integration and especially on TSV sidewalls, requiring sufficient step coverage.
Ionized PVD is today widely extended from BEOL to TSV metallization. This technique has, however , several limitations for 3D integration coming from its poor step coverage in 10:1 aspect ratio features thus requiring thick material deposition to cover sidewalls which will lead to expensive process both for deposition and further CMP steps and high stress leading to adhesion issues.
Considering the maturity level of the alternative processes, MOCVD metallization appears to be a very promising Solution. MOCVD TiN layers have been widely reported to provide excellent step coverage and diffusion barrier efficiency in BEOL processes.
The presented study describes a process based on an MOCVD TiN deposition that can be performed from 175 to 400 °C. This polyvalent process can be performed for anytype of 3D integration from Mid process TSVs where performance is the key factor to Via last integration for which low temperature and low cost processes are required.
The paper will first discuss the process development and characterization of this material with particular focus on key parameters for 3D integration. In addition, film integration in Via-Middle TSVs will be described, comparing step coverage performance in high aspect ratio TSVs with the I-PVD reference process.
Then, electrical measurements of daisy chains and interconnect lines from a 300 mm 3D demonstrator will be presented.
A Study on the Seed Step-coverage Enhancement Process (SSEP) of High Aspect Ratio Through Silicon Via (TSV) Using Pd/Cu/PVP Colloids