Advanced Atomic Layer Deposition Technologies for Micro-LEDs and VCSELs

In recent years, the process requirements of nano-devices have led to the gradual reduction in the scale of semiconductor devices, and the consequent non-negligible sidewall defects caused by etching. Since plasma-enhanced chemical vapor deposition can no longer provide sufficient step coverage, the characteristics of atomic layer deposition ALD technology are used to solve this problem. ALD utilizes self-limiting interactions between the precursor gas and the substrate surface. When the reactive gas forms a single layer of chemical adsorbed on the substrate surface, no reaction occurs between them and the growth thickness can be controlled. At the Å level, it can provide good step coverage. In this study, recent research on the ALD passivation on micro-light-emitting diodes and vertical cavity surface emitting lasers was reviewed and compared. Several passivation methods were demonstrated to lead to enhanced light efficiency, reduced leakage, and improved reliability.

Conformal and Smooth TiN Film Growth by using Variable-Pressure Thermal ALD Method

Better TiN film quality such as lower roughness and higher step coverage is required in recent semiconductor devices as the semiconductor device is scaled down. In this study, highly conformal ALD TiN film with excellent step coverage was achieved by using variable-pressure deposition method. TiN film grown at low-pressure condition was more conformal and smoother than that grown at high-pressure condition, although step coverage value grown at low-pressure condition was worse than that grown at high-pressure condition. By optimizing low/high pressure two-step TiN growth condition, it was achieved that not only better roughness than that of pure high-pressure TiN, but also, better step coverage value than that of pure low-pressure TiN as well as than that of pure high-pressure TiN.

Preparation of iridium metal films by spray chemical vapor deposition

Metal Ir films were prepared by spray chemical vapor deposition (CVD) in air from an Ir precursor, (1,3-cyclohexadiene)(ethylcyclopentadienyl)iridium, Ir(EtCp)(CHD). Film deposition was ascertained at 270–430°C on a SiO2/Si substrate and the deposition rate increased with the deposition temperature but was saturated above 330°C. The obtained films consisted of Ir metal without any iridium oxide impurity irrespective of the deposition temperature. Films tended to orient to (111) with increasing deposition temperature. Resistivity of these Ir films decreased with increasing film thickness and reached to values on the order of 10-6 Ω・cm, which was the same order of the values for bulk Ir metal. Good step coverage was observed for the Ir metal films deposited at 270°C and 330°C. This shows that the simple spray CVD process in air is a good candidate for depositing Ir metal films with good conductivity and step coverage.

Remote Plasma Atomic Layer Deposition of SiNx Using Cyclosilazane and H2/N2 Plasma

Silicon nitride (SiNx) thin films using 1,3-di-isopropylamino-2,4-dimethylcyclosilazane (CSN-2) and N2 plasma were investigated. The growth rate of SiNx thin films was saturated in the range of 200–500 °C, yielding approximately 0.38 Å/cycle, and featuring a wide process window. The physical and chemical properties of the SiNx films were investigated as a function of deposition temperature. As temperature was increased, transmission electron microscopy (TEM) analysis confirmed that a conformal thin film was obtained. Also, we developed a three-step process in which the H2 plasma step was introduced before the N2 plasma step. In order to investigate the effect of H2 plasma, we evaluated the growth rate, step coverage, and wet etch rate according to H2 plasma exposure time (10–30 s). As a result, the side step coverage increased from 82% to 105% and the bottom step coverages increased from 90% to 110% in the narrow pattern. By increasing the H2 plasma to 30 s, the wet etch rate was 32 Å/min, which is much lower than the case of only N2 plasma (43 Å/min).

Advanced barrier and seed layer deposition enabling multiple type of TSVs integration

TSV integration is a key technology allowing heterogeneous devices 3D integration. However, depending on the targeted application, various TSV sizes and integration schemes exist, all requesting very high aspect ratio. The most common integration is the Mid-process TSV for which aspect ratio is required to be higher than 10:1 whatever application. In the case of large interposers, silicon thickness has to be increased to limit the deformation of the substrate due to highly stressed devices. Same requirements are made by photonic interposers which use thick SOI substrate leading to high warpage during integration. In the opposite, imagers requires to save silicon surface thus reduce TSV size and keep out zone. Silicon thickness has to be kept in the 100 μm range leading then the aspect ratio of the TSV to increase. Recently, Hybrid bonding progresses allowed a new type of TSV to be introduced : High Density TSVs for imagers. In this application, micrometer range TSV have to be filled with a Silicon thickness reduction limited to 10 μm by grinding process control. In order to allow the metal filling of all those type of structures, we have developed a highly conformal barrier and seed layer processes using standard materials for easier integration. The process is based on the use of MOCVD TiN as a barrier. This material is deposited using TDMAT precursor which allows low temperature deposition (200 °C)[1] which extends also the polyvalence of the process toward polymer bonded integrations. The very high step coverage of this process, reported at more than 30% in 20:1 aspect ratio coupled to high resistance to copper diffusion allows as thin as 20 nm barrier thickness which appears relevant economically (for deposition and CMP) and for stress consideration, compared to the well known but thicker PVD TaN process. Considering seed layer, the eG3D process[2] was brought to a high maturity allowing it to be integrated in an applied material raider tool coupled to TSV filling reactors. This process, based on electrografting of copper has already proved a step coverage of more than 50% in 12:1 aspect ratio structures. The presented work shows that the same process requires only deposition parameters change to be able to fully cover 10×150 μm Mid-process TSV as well as 1×10 μm High density ones. The excellent step coverage of this process allowed as thin as 200 nm (for 10×120 μm TSVs) and 100 nm (for (1×10 μm ones) deposited thicknesses to ensure perfect coverage of the structures. eG3D process also has the ability to be used as a repair process for non-continuous widely used PVD Cu seed layers but also be deposited directly on the barrier material. These 2 layers were evaluated together in a 300mm TSV integration schemes of both 10×120 mid process and 1×10 μm High Density structures and qualified electrically. The paper will discuss the deposition process development leading to simultaneously allow copper filling of the very wide range of TSVs on the same process equipment and using the same chemicals. We will then present integration results as well as electrical test of TSV daisy chains of both mid and High density TSVs showing excellent yield for all TSV size and integration schemes.