Minimizing GPS Clock Synchronization Error for PX4-Based Unmanned Aircraft

The sampling rate at a given bit rate is a requirement for the speed of digital signal processors. In this regard, it is necessary to strive to reduce it in the development of electronic devices, especially portable ones. However, this can lead to an increase in the bit error rate during signal detection. Therefore, it is important to determine the degradation of signal detection with decreasing sampling frequency and to develop practical recommendations to ensure the specified quality of communication. The aim of the article is to study the influence of sampling frequency and interpolation on the bit error rate of GMSK Signal. The article considers the incoherent detection of a GMSK signal in a channel with additive white Gaussian noise, taking into account the influence of the clock synchronization error. Numerical results are presented that characterize an increase in the bit error rate with a decrease in the signal sampling frequency. It is shown that when using the cubic Farrow interpolator, there is no significant degradation in the bit error probability. The minimum number of samples per symbol is determined, at which the bit error rate is close to the theoretical values in the absence of synchronization error. The presented results can be used in development of wireless data transmission systems.

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Clock synchronization error compensation algorithm based on BP neural network model

Acta Physica Sinica ◽

10.7498/aps.70.20201641 ◽

2021 ◽

Vol 70 (11) ◽

pp. 114203-114203

Author(s):

Wei Lian-Suo ◽

◽

Li Hua ◽

Wu Di ◽

Guo Yuan

Keyword(s):

Neural Network ◽

Network Model ◽

Neural Network Model ◽

Bp Neural Network ◽

Error Compensation ◽

Clock Synchronization ◽

Synchronization Error ◽

Compensation Algorithm ◽

Bp Neural Network Model

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A Fractional Order Control and Correction Strategy for EtherCAT Communication Clock Drift

10.1115/detc2021-70814 ◽

2021 ◽

Author(s):

Jihao Sun ◽

Pengchong Chen ◽

Ying Luo

Keyword(s):

Fractional Order ◽

Clock Synchronization ◽

Synchronization Error ◽

Crystal Oscillator ◽

Loop Control ◽

Clock Drift ◽

Proportional Integral ◽

Synchronization Problem ◽

Control Automation ◽

Reference Clock

Abstract Ethernet Control Automation Technology (EtherCAT) applies distributed clock (DC) to realize synchronization among different slaves. Due to the influence of the crystal oscillator manufacturing process and environment, there is still synchronization error between reference clock and non-reference clock. To solve the clock synchronization problem, this paper proposes a clock drift compensation algorithm based on the idea of closed-loop control. By designing integer-order proportional integral (IOPI) and fractional-order proportional integral (FOPI) controllers, the synchronization error between slaves can be minimized. The IOPI and FOPI controllers designed in this paper are used to eliminate the drift error. This method improves the synchronization accuracy without bringing too much computational load. The results show that the proposed FOPI controller can effectively reduce the synchronization error with even better performance over the IOPI controller.

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Clock Synchronization in Wireless Sensor Networks: Analysis and Design of Error Precision Based on Lossy Networked Control Perspective

Mathematical Problems in Engineering ◽

10.1155/2015/346521 ◽

2015 ◽

Vol 2015 ◽

pp. 1-17 ◽

Cited By ~ 2

Author(s):

Wang Ting ◽

Guo Di ◽

Cai Chun-yang ◽

Tang Xiao-ming ◽

Wang Heng

Keyword(s):

Wireless Sensor Networks ◽

Sensor Networks ◽

Packet Loss ◽

Information Exchange ◽

Clock Synchronization ◽

Error Variance ◽

Synchronization Error ◽

Wireless Sensor ◽

Analysis And Design ◽

Packet Arrival

Motivated by the importance of the clock synchronization in wireless sensor networks (WSNs), due to the packet loss, the synchronization error variance is a random variable and may exceed the designed boundary of the synchronization variance. Based on the clock synchronization state space model, this paper establishes the model of synchronization error variance analysis and design issues. In the analysis issue, assuming sensor nodes exchange clock information in the network with packet loss, we find a minimum clock information packet arrival rate in order to guarantee the synchronization precision at synchronization node. In the design issue, assuming sensor node freely schedules whether to send the clock information, we look for an optimal clock information exchange rate between synchronization node and reference node which offers the optimal tradeoff between energy consumption and synchronization precision at synchronization node. Finally, simulations further verify the validity of clock synchronization analysis and design from the perspective of synchronization error variance.

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Research on IEEE 1588 Clock Synchronization Error Correction Algorithm Based on Kalman Filter

Journal of Physics Conference Series ◽

10.1088/1742-6596/1449/1/012109 ◽

2020 ◽

Vol 1449 ◽

pp. 012109

Author(s):

Rongbin Ju ◽

Rongmao Wang ◽

Peng Yu ◽

Rong Chen ◽

Shunjiang Wang ◽

...

Keyword(s):

Kalman Filter ◽

Error Correction ◽

Clock Synchronization ◽

Synchronization Error ◽

Correction Algorithm ◽

Ieee 1588 ◽

Error Correction Algorithm

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FC Network Clock Synchronization Error Analysis and Solution

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.380-384.2204 ◽

2013 ◽

Vol 380-384 ◽

pp. 2204-2208

Author(s):

Wang Jin Ping ◽

Wen Jing

Keyword(s):

Error Analysis ◽

Influencing Factors ◽

Clock Synchronization ◽

Synchronization Error ◽

Paper Briefly ◽

Error Sources ◽

Avionic System

The clock synchronization is the foundation of other applications in the FC network to support the avionic system. This paper briefly elaborates the clock synchronization in the fabric topology which is widely used in FC. According to the implementation of the clock synchronization, the paper emphatically analyzes the error sources and influencing factors existed in the processing of the clock synchronization, moreover, puts forward the solutions for the corresponding errors. Finally, an example is provided to show the consequence of the error analysis.

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